JPH03101432A - Data reception circuit - Google Patents

Abstract

PURPOSE:To prevent erroneous data from being reproduced by extracting the timing component of a data signal at a reception side and reproducing the data. CONSTITUTION:When a transmission side sends the data signal and a clock signal, the data signal is inputted to an input terminal 1 and connected to the data input section of a flip-flop 4. On the other hand, the clock signal is inputted to an input terminal 2 and a timing extraction circuit extracts the timing and its output signal is converted into a TTL level at a rectangular wave conversion circuit 6, connected to the clock input section of a flip-flop 4 and the data signal is regenerated. Thus, no noise pulse or distorted clock exists in the clock signal due to crosstalk between signal lines and the data signal is regenerated without error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data receiving circuit for receiving digital signals between packages in a digital transmission device.

[Conventional technology]

Conventionally, this type of data receiving circuit transmits a clock signal along with a data signal on the transmitting side, and connects the transmitted data signal to a data input terminal of a flip-flop on the receiving side 7, and receives the transmitted clock signal. It was connected to the clock input terminal of a flip-flop to reproduce the waveform of sent data and perform digital transmission.

[Problem to be solved by the invention]

In the conventional data receiving circuit described above, in order to perform digital transmission between the packages in the device, a means to connect the transmitted and received signals between the packages is required. There is a way to use a backboard to connect. Since multiple signal lines coexist on the wiring or backboard that connects packages, crosstalk occurs between each signal line, and noisy pulses are also generated in the clock signal sent from the transmitting side. Or, the clock signal may be affected. Therefore, if a flip-flop circuit is driven with a clock signal affected by crosstalk, the flip-flop circuit has the disadvantage that incorrect data will be reproduced.

[Means to solve the problem]

The data receiving circuit of the present invention includes a flip-flop circuit that inputs a data signal and a clock signal, a timing extraction circuit that extracts and outputs the timing component of the data signal, and converts the output from the timing extraction circuit into a rectangular wave. and a rectangular wave conversion circuit that generates the clock signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

1 and 2 are block diagrams of first and second embodiments of the present invention.

The first and second embodiments include a flip-flop 71 circuit 4.13 to which data signals from input terminals 1 and 11 are input, and a timing extraction circuit 5.14 to which a clock signal having a timing component of the data signal is input. , a rectangular wave conversion circuit 6, 1 that converts the output signal of the timing extraction circuit into a rectangular wave.
5, and the output signals of the rectangular wave conversion circuits 6 and 15 are connected to the clock input section of a flip-flop 4.degree. 14.

Next, the operation will be explained.

A first embodiment of the present invention is a case in which a data signal and a clock signal are sent from the transmitting side in FIG. Ru.

On the other hand, the clock signal is input to the input terminal 2, the timing is extracted by the timing extraction circuit 5, the output signal is converted to a TTL level by the rectangular wave conversion circuit 6, and is connected to the clock input part of the flip-flop 4 to be used as data. Regeneration of the signal takes place.

A second embodiment of the present invention is shown in FIG. 2, in which the data signal is transmitted from the transmitting side in a coded format that allows extraction of the timing included in the data signal, and the data signal is sent from the input terminal 11.
The signal is input from the data input section of the flip-flop circuit 13 and the timing extraction circuit 14 . A timing extraction circuit 14 extracts timing from the data signal, converts it to a TTL level in a rectangular wave conversion circuit 15, and connects to a clock input section of a flip-flop circuit 13 to reproduce the data signal.

〔Effect of the invention〕

As explained above, the present invention extracts and reproduces the timing component of a data signal on the receiving side, thereby allowing
This has the effect of eliminating noisy pulses or clock divisions in the tarlock signal caused by crosstalk between the mixed signal lines, and thereby reproducing the data signal without error.

[Brief explanation of drawings]

1 and 2 are block diagrams of first and second embodiments of the present invention. 1.2.11...Input terminal, 3.12...Output terminal, 4.13...Flip-flop circuit, 5,14...
- Timing extraction circuit, 6.15. ...Square wave generation circuit.

Claims (1)

[Claims] A flip-flop circuit that inputs a data signal and a clock signal, a timing extraction circuit that extracts and outputs the timing component of the data signal, and a rectangle that converts the output from the timing extraction circuit into a rectangular wave and generates the clock signal. A data receiving circuit comprising: a wave conversion circuit.