JPS6088651U - Digital multiplex converter - Google Patents
Digital multiplex converterInfo
- Publication number
- JPS6088651U JPS6088651U JP18117383U JP18117383U JPS6088651U JP S6088651 U JPS6088651 U JP S6088651U JP 18117383 U JP18117383 U JP 18117383U JP 18117383 U JP18117383 U JP 18117383U JP S6088651 U JPS6088651 U JP S6088651U
- Authority
- JP
- Japan
- Prior art keywords
- transmitting side
- input signal
- input
- detected
- normal use
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Time-Division Multiplex Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の実施例に係るデジタル多重変換装置の
構成を示すブロック図である。
１・・・・・・Ｄ型フリップフロップ回路（［）−ＦＦ
）、２・・・・・・クロック入力端子、３〜８・・・・
・・２人力ＮＡＮＤ回路、９，１０・・・・・・インバ
ータ回路、１１・・・・・・マルチプレクサ−１１２・
・・・・・多重化信号出力端子、１３，１４・・・・・
・送信側入力断信号端子、１５．１６・・・・・・送信
側信号入力端子、１７・・・・・・抵抗、１８・・・・
・・スイッチ。FIG. 1 is a block diagram showing the configuration of a digital multiplex converter according to an embodiment of the present invention. 1...D type flip-flop circuit ([)-FF
), 2... Clock input terminal, 3 to 8...
...2-manpower NAND circuit, 9, 10... Inverter circuit, 11... Multiplexer 112...
...Multiplexed signal output terminal, 13, 14...
・Sending side input disconnection signal terminal, 15.16...Sending side signal input terminal, 17...Resistor, 18...
··switch.
Claims (1)
うデジタル多重変換装置において、通常使用時には所定
のパルスを出力し、試験時には一定の論理レベルを出力
することを可能とする切換スイッチを有する発振回路と
、 通常使用時で送信側の入力信号が入力するときはこれを
検知してそのまま出力し、送信側の入力信号が無人力の
ときこれを検知して前記発振回路の所定のパルスを出力
するとともに、試験時で送信側の入力信号が無人力のと
きこれを検知して前記発振回路の一定論理レベルを出力
する論理ゲート回路と、 ° 通常使用時には前記送信側の入力信号または前記
所定のパルスを入力してこれを多重化し、試験時には前
記一定論環レベルを検知してフレームパルス等の基準パ
ルスを自己発生することを可能と、するマルチプレクサ
−によって構成されたことを特徴とするデジタル多重変
換装置。[Claims for Utility Model Registration] A digital multiplex converter that multiplexes and inversely converts multiple digital input signals, capable of outputting predetermined pulses during normal use and outputting a constant logic level during testing. In normal use, when the input signal on the transmitting side is input, it is detected and outputted as is, and when the input signal on the transmitting side is unattended, it is detected and the oscillation circuit has a changeover switch. a logic gate circuit that outputs a predetermined pulse of the circuit, detects when the input signal on the transmitting side is unattended during testing, and outputs a constant logic level of the oscillation circuit; ° During normal use, the transmitting side; The input signal or the predetermined pulse is input and multiplexed, and during testing, the constant logic level is detected and reference pulses such as frame pulses can be self-generated. A digital multiplex conversion device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18117383U JPS6088651U (en) | 1983-11-24 | 1983-11-24 | Digital multiplex converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18117383U JPS6088651U (en) | 1983-11-24 | 1983-11-24 | Digital multiplex converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6088651U true JPS6088651U (en) | 1985-06-18 |
| JPH0119484Y2 JPH0119484Y2 (en) | 1989-06-06 |
Family
ID=30392652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18117383U Granted JPS6088651U (en) | 1983-11-24 | 1983-11-24 | Digital multiplex converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6088651U (en) |
-
1983
- 1983-11-24 JP JP18117383U patent/JPS6088651U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0119484Y2 (en) | 1989-06-06 |
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