JPS5961680U - Time division multiplex transmission system - Google Patents

Time division multiplex transmission system

Info

Publication number
JPS5961680U
JPS5961680U JP15675582U JP15675582U JPS5961680U JP S5961680 U JPS5961680 U JP S5961680U JP 15675582 U JP15675582 U JP 15675582U JP 15675582 U JP15675582 U JP 15675582U JP S5961680 U JPS5961680 U JP S5961680U
Authority
JP
Japan
Prior art keywords
signal
control data
address
terminal
time division
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15675582U
Other languages
Japanese (ja)
Other versions
JPH0122300Y2 (en
Inventor
秋葉　修
義春 鈴木
寺田　元治
隆 佐伯
Original Assignee
松下電工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電工株式会社 filed Critical 松下電工株式会社
Priority to JP15675582U priority Critical patent/JPS5961680U/en
Publication of JPS5961680U publication Critical patent/JPS5961680U/en
Application granted granted Critical
Publication of JPH0122300Y2 publication Critical patent/JPH0122300Y2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のブロック図、第２図は本考案の一実施例
のブロック図、第３図は同上の伝送波形のフォーマット
を示す図である。 １は親機、２は信号線、３は端末器、４はロー−カルシ
ステム、６はパラレル入出力インタフェイス、７はクリ
アモード検出回路、Ｒ工〜Ｒ６はバッファメモリである
。FIG. 1 is a conventional block diagram, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a diagram showing the format of the transmission waveform. 1 is a base unit, 2 is a signal line, 3 is a terminal device, 4 is a local system, 6 is a parallel input/output interface, 7 is a clear mode detection circuit, and R to R6 are buffer memories.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 親機と複数個の端末器とを１対の信号線を介して互いに
接続し、親機から各端末器に対してアドレス信号と制御
データ信号と返送待機信号とを含む信号を伝送し、各端
末器には信号線上のアドレス信号と自己のアドレスとの
一致時に制御データ信号に応じた制御出力を生じる制御
データ出力端と、返送待機信号の期間中に、信号線を介
して親パ′機の側に返送する監視信号を入力する監視信
号入力端とを設けて成る時分割多重伝送システムにおい
て、端末器を介して親機により監視制御される被監視制
御器のパラレル入出力インターフェイスと端末器との間
に、ハンドシェイク方式によるデータ送受のタイミング
を制御する信号を一時記憶するバッファメモリを設ける
と共に、親機から伝送されるクリアモード信号め検出時
に上記バッファメモリの記憶内容をクリアするクリアモ
ード検出回路を設けて成る時分割多重伝送システム。A base unit and multiple terminals are connected to each other via a pair of signal lines, and signals including an address signal, a control data signal, and a return standby signal are transmitted from the base unit to each terminal, and each The terminal device has a control data output terminal that generates a control output according to the control data signal when the address signal on the signal line matches its own address, and a control data output terminal that outputs a control output according to the control data signal when the address signal on the signal line matches its own address. In a time division multiplex transmission system, the parallel input/output interface of a monitored controller that is monitored and controlled by a parent device via a terminal device and a supervisory signal input terminal for inputting a supervisory signal to be sent back to the terminal device. A buffer memory for temporarily storing signals that control the timing of data transmission and reception using the handshake method is provided between the main unit and a clear mode that clears the contents of the buffer memory when a clear mode signal transmitted from the base unit is detected. A time division multiplex transmission system equipped with a detection circuit.
JP15675582U 1982-10-15 1982-10-15 Time division multiplex transmission system Granted JPS5961680U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15675582U JPS5961680U (en) 1982-10-15 1982-10-15 Time division multiplex transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15675582U JPS5961680U (en) 1982-10-15 1982-10-15 Time division multiplex transmission system

Publications (2)

Publication Number Publication Date
JPS5961680U true JPS5961680U (en) 1984-04-23
JPH0122300Y2 JPH0122300Y2 (en) 1989-06-30

Family

ID=30345791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15675582U Granted JPS5961680U (en) 1982-10-15 1982-10-15 Time division multiplex transmission system

Country Status (1)

Country Link
JP (1) JPS5961680U (en)

Also Published As

Publication number Publication date
JPH0122300Y2 (en) 1989-06-30

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