JPH0119484Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an operation test circuit for a digital multiplex converter.

[Background technology]

In order to investigate whether the digital multiplex converter is operating normally, it is necessary to check whether frame pulses and the like are correctly generated and inserted. In this case, the input data must be fixed to zero. In conventional devices, it was possible to fix the signal to zero by turning off the input signal on the transmitting side, depending on the configuration of the device itself.

However, when the digital multiplex converter is in use, an alarm is issued when the input signal is disconnected.
It is designed to notify the operator of malfunctions, etc. However, in such a digital multiplex conversion device, when the input signal on the transmitting side is disconnected, the opposite device on the receiving side also detects the disconnection, and both sides issue an alarm. For this reason,
There were times when I was confused because I didn't know which device had the problem. Therefore, when the input signal is disconnected, the digital multiplex converter is configured to automatically generate and insert a pseudo signal instead of fixing it to zero, so that it is possible to know at what stage the input signal is disconnected.

However, in such a configuration, it is not possible to fix the input data to zero simply by cutting off the input, which is inconvenient when testing the generation and insertion of frame pulses, etc., as described above.

[Purpose of invention]

The present invention was proposed in view of the above points, and in normal use, input signals are input and digitally multiplexed, and when the input signal is disconnected, frame pulses etc. are generated to enable testing of the device. The purpose of this invention is to provide a digital multiplex conversion device.

[Structure of the idea]

The digital multiplex converter of this invention consists of an oscillator circuit with a changeover switch that outputs a predetermined pulse during normal use and a fixed logic level during testing, and an input signal on the transmitting side during normal use. When the input signal is input, it is detected and output as is, and when the input signal on the transmitting side is not input, it is detected and the predetermined pulse of the oscillation circuit is output. A logic gate circuit detects this when there is no input and outputs a constant logic level of the oscillation circuit, and a logic gate circuit that inputs and multiplexes the input signal of the transmitting side or the predetermined pulse during normal use, and the The multiplexer detects a certain logic level and automatically generates a reference pulse such as a frame pulse.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a digital multiplex conversion circuit according to an embodiment of the present invention. 1
is a D-type flip-flop circuit (hereinafter referred to as D-FF). Its reset input is connected to the power supply VDD via a resistor 17, and is also connected to a selector switch 18.
is grounded through. This changeover switch 18
Therefore, in the test state (TST in the figure), the reset input is set to "L" level and the Q output of D-FF1 is fixed to "L" level. On the other hand, in the normal use state (NOR in the figure), the reset input is set to the "H" level and the D-FF1 becomes capable of clock operation. Reference numeral 2 designates a clock terminal to which a reference clock pulse is input, and since the Q output and D input are connected, a 1/2 frequency divided pulse is output from the Q output of D-FF1 in the normal operating state.

3 is a 2-input NAND circuit, one input of which is connected to the Q output of D-FF 1, and the other input connected to the transmitting side input disconnection signal terminal 13. 4 also 2 inputs
It is a NAND circuit, one input of which is connected to the transmission side input disconnection signal terminal 13 via the inverter circuit 9, and the other input connected to the transmission side input terminal 15.
Signals to be multiplexed are input to this transmitting side input terminal 15. On the other hand, the transmitting side input disconnection signal terminal 1
3, when the signal to be multiplexed is input to the transmitting side input terminal 15, a signal in the "L" level state is input, and when the signal to be multiplexed is not input, that is, when the signal is disconnected. A signal in the H'' level state is input. 5 is a 2-input NAND circuit, and 2-input NAND circuits 3 and 4
The output of is used as input.

In the figure, circuits 6, 7, 8 and terminals 14, 1
6 is the aforementioned circuit 3, 4, 5 and terminal 13, 1
5 and have similar functions.

11 is a multiplexer with 2 inputs
When there are signal outputs from the NAND circuits 5 and 8, these are multiplexed, and when the signal outputs are at the "L" level, only the frame pulses and the like that are generated by themselves are outputted from the output terminal 12.

Next, a digital multiplex conversion device according to an embodiment of the present invention will be described. D-FF in normal use condition
A predetermined pulse is input from the Q output of 1 to one input of the 2-input NAND circuits 3 and 6. In this state, when a predetermined input signal is input to the transmitting side input terminals 15 and 16, the transmitting side input disconnection signal terminals 13 and 14
Since the signal state of is at "L" level, the above input signal is sent to the two-input NAND circuits 4, 7 and 5,
The signal is input directly to the multiplexer 11 via 8. The multiplexer multiplexes these signals and outputs the multiplexed signal from output terminal 12.
If a predetermined input signal is not input to the transmitting side input terminals 15 and 16, that is, when it is disconnected, the signal state of the transmitting side input disconnection signal terminals 13 and 14 is at the "H" level state, so the two-input NAND circuit 4 , 7 is in the "L" level state, and the pulse signal from the Q output of D-FF1 is sent to the 2-input NAND circuit 3.
and 5 to be directly input to the multiplexer 11. That is, even if the input signal on the transmitting side is disconnected, the multiplexer 11 can receive a pseudo pulse signal instead of a disconnection signal.

When a test state is desired, the selector switch 18 is switched to the test side. As a result, the Q of D-FF1
The output is fixed at the "L" level state. Further, in the test state, since the transmitting side input disconnection signal terminals 13 and 14 are in the "H" level state, the outputs of the two-input NAND circuits 5, 8 are fixed at the "L" level state.
Therefore, the multiplexer 11 outputs only the frame pulses generated by itself from the output terminal 12. This makes it easy to test whether frame pulses, etc. are generated and inserted correctly.

[Effect of idea]

As explained above, according to the present invention, even when the signal is cut off in the normal use state, the receiving side output cut-off prohibition pattern is input and the input cut-off is prevented. is entered,
This is extremely convenient because frame pulses and the like are generated and inserted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a digital multiplex converter according to an embodiment of the present invention. 1...D-type flip-flop circuit (D-FF),
2...Clock input terminal, 3-8...2 inputs
NAND circuit, 9, 10... Inverter circuit, 1
1... Multiplexer, 12... Multiplexed signal output terminal, 13, 14... Transmission side input disconnection signal terminal,
15, 16...Sending side signal input terminal, 17...Resistor, 18...Switch.

Claims (1)

[Claims for Utility Model Registration] A digital multiplex converter that multiplexes and inversely converts multiple digital input signals, capable of outputting predetermined pulses during normal use and outputting a constant logic level during testing. In normal use, when an input signal on the transmitting side is input, it is detected and output as is, and when no input signal on the transmitting side is input, it is detected and the oscillation circuit has a changeover switch. a logic gate circuit that outputs a predetermined pulse of the circuit, detects when no input signal is input on the transmitting side during testing, and outputs a constant logic level of the oscillation circuit; A multiplexer that inputs and multiplexes an input signal or the predetermined pulse, detects the predetermined logic level during testing, and can automatically generate a reference pulse such as a frame pulse. A digital multiplex conversion device characterized by: