JPH05304461A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the floating of a bus when whole three state outputs become disenable by connecting a data holding circuit consisting of two inverter circuits to the bus in bus structure where a plurality of the outputs of three state logic circuits are mutually connected. CONSTITUTION:A data holding circuit 4 where the respective outputs of the two inverters 5 are mutually connected to the each input of the other inverter is connected to bus structure which is constituted of plural bus drivers 1 of three state logic circuits whose outputs are mutually connected and plural bus receivers 2 for receiving output data of the bus drivers 1. When the whole circuits of the plural bus drivers 1 become enable, the bus 6 is held in an output data level immediately before the whole bus drivers 1 become disenable, that is, the output data level which is outputted when only one circuit of the bus drivers 1 is enable.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to semiconductor integrated circuits, and more particularly,
The present invention relates to a semiconductor integrated circuit having a bus structure in which at least two outputs of a 3-state logic circuit are connected.

[0002]

2. Description of the Related Art A conventional bus structure comprises a plurality of bus drivers 1 which are 3-state logic circuits having outputs connected to each other as shown in FIG. 2 and a bus receiver 2 which receives output data from the bus driver 1. Further, as shown in FIG. 3, the bus may be connected to the power supply or the ground via the resistor 3.

Next, the operation will be described. In the case of the bus structure shown in FIG. 2, only one of the plurality of bus drivers 1 is enabled (logic “1” or logic “0” output), and all other circuits are disabled (high impedance output). Then, the logical data is transmitted to the bus receiver 2. In the case of the bus structure shown in FIG. 3, in addition to the operation of the bus structure shown in FIG. 2, when all the plurality of bus drivers 1 are disabled, a logic “1” or logic There is an operation that is clamped to "0".

[0004]

In this conventional semiconductor integrated circuit, in the case of FIG. 2, when all the bus drivers 1 are disabled, the bus becomes floating and the logic becomes uncertain. In the case of a circuit, since the input level of the bus receiver 2 is indefinite, a through current flows through the bus receiver 2 and there is a problem in reliability.

Further, in the case of FIG. 3, even if all the bus drivers 1 are disabled, the buses are not floated because they are clamped to the power supply or the ground via the resistors 3, but the bus driver 1 There is a problem that a steady current flows through the resistor 3 when any one of them is enabled and outputs either the logic "1" or the logic "0".

[0006]

According to the semiconductor integrated circuit of the present invention, a data holding circuit in which each output of two inverter circuits is connected to each input of another inverter is connected to a bus.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.
The outputs of the two inverters 5 are connected to each other by a bus structure constituted by a plurality of bus drivers 1 which are three-state logic circuits whose outputs are connected to each other and a bus receiver 2 which receives output data of the bus driver 1. The data holding circuit 4 connected to each input of is connected.

When only one circuit of the plurality of bus drivers 1 is enabled and all other circuits are disabled, the output data of the enabled circuits is transmitted to the bus receiver 2. At that time, the data held in the data holding circuit 4 changes according to the change in the output data. Next, when all the circuits of the plurality of bus drivers 1 are disabled, the bus 6 immediately before the bus holding circuits 4 are disabled by the data holding circuit 4, that is, one of the bus drivers 1
It is held at the level of the output data that was being output when only the circuit was enabled.

[0010]

As described above, according to the present invention, since the data holding circuit is connected to the bus, the bus does not become floating even when all the bus drivers are disabled, and there are a plurality of bus drivers. One of the circuits is enabled, and there is an effect that a steady current does not flow depending on the level of logic data even when transmitting data.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a first conventional example.

FIG. 3 is a circuit diagram showing a second conventional example.

[Explanation of symbols]

 1 bus driver 2 bus receiver 3 resistor 4 data holding circuit 5 inverter

Claims (1)

[Claims] 1. A bus used by connecting at least two or more outputs of a logic circuit (hereinafter referred to as a three-state logic circuit) having three kinds of output levels of a digital circuit: logic "1", logic "0", and high impedance. A semiconductor integrated circuit having a structure, wherein a data holding circuit in which each output of two inverter circuits is connected to each input of another inverter is connected to a bus.