JPH06237159A - Signal input circuit - Google Patents

Abstract

PURPOSE:To attain stable circuit operation by providing a means detecting it that all signal lines go to H (all H) and a means letting an output of a latch-up circuit be an L level when all H is first detected by the detection means after application of power source and keeping the L state so as to shorten voltage level uncertainly time at the time of application of power source. CONSTITUTION:Just after application of power source, since a signal at a point A produced by a resistor Rr, Cr and a Schmitt buffer 5 remains at an L level, the signal at the point A is inputted to a CLR of a D flip-flop 6 to let an output (signal at a point C) of the flip-flop 6 go to H and output levels of D0'-Dn' (signal input terminal 3) all go to H via an OR circuit 4. That is, just after application of power source, the level of the data buses D0'-Dn' is set to H. When the signal at the point A and the signals of D0-Dn all go to H, a signal at a point C goes to an L level. Thus, the signal levels of the D0-Dn go to the signal levels of the D0'-Dn' (signal input terminal 3) as they are.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal input circuit having a data bus line and a data latch circuit that are pulled up when there is no signal, and more particularly to a circuit for stabilizing an initial voltage level when power is turned on.

[0002]

2. Description of the Related Art Generally, in order to fix voltage levels of signal lines (data buses) D _{1 to} D _n for negative logic data, FIG.
As shown in (A), Vcc is connected via the pull-up resistor R. In case of data latch circuit, output terminal Q
In order to stabilize the voltage level of the resistor immediately after the power is turned on, a direct preset (or reset) circuit including a resistor Rr, a capacitor Cr, and a Schmitt buffer 11 is configured as shown in FIG. Signal using time constant (potential at point A in FIG. 4 (A) = FIG. 4 (B))
A signal obtained by shaping the solid line) by the Schmitt buffer 11 (potential at point B in FIG. 4A = dashed line in FIG. 4B) is input to the preset terminal PR of the flip-flop 12. As a result, the output of the output terminal Q becomes "H" almost immediately after the power is turned on.

[0003]

When the voltage level of the data bus is fixed by the pull-up resistor as described above, in addition to the pull-up resistor R as shown in FIG. There is a load C such as wiring capacitance on the board. Therefore, when the power is turned on, the voltage rises gently, and as shown in FIG. 3B, it takes some time T for the voltage level to stabilize. Therefore, if an operation to read the data on the data buses D _{1 to} D _n occurs during this time T, there is a possibility that wrong data may be taken in.

In the case of the data latch circuit, the initial unstable state can be shortened by giving a direct preset (or reset) signal to the flip-flop 12, but for the same reason as the case of the data bus shown in FIG. It takes a time T until the data input signal Da and the clock input signal CK of the flip-flop are fixed. Here, the preset (or reset) signal width (see FIG.
T is the time until the potential at point B in (A) becomes "H".
Assuming that there is a state where T> Tr as shown in FIG. 2C, and C is set after the preset (reset) release time Tr.
K may rise (“L” → “H”). At this time, if the voltage level of Da is not sufficient, an uncertain value is taken in, and the potential of the Q output that should maintain the "H" level as shown by the solid line in FIG. There is a risk of falling to the "L" level.

In view of the above problems, it is an object of the present invention to provide a signal input circuit for shortening the voltage level uncertain time at power-on and realizing stable circuit operation.

[0006]

According to the present invention, a signal line and a latch-up circuit are connected to a signal input terminal, and
Detecting means for detecting that all the signal lines have become "H" (hereinafter referred to as all "H"), and the latch-up circuit of the latch-up circuit when the detecting means detects all "H" for the first time after power-on. Means for keeping the output "L" and maintaining the "L" state.

[0007]

In the signal input circuit of the present invention, the voltage level of the signal line gradually rises when the power is turned on.
The voltage level of the latch-up circuit becomes "H" immediately after the power is turned on. Therefore, the signal from the latch-up circuit is input to the signal input terminal, and the voltage level of the signal input terminal becomes "H" almost immediately after the power is turned on. on the other hand,
When the voltage level of the signal line gradually rises and becomes stable to all "H", the detecting means detects this, the output of the latch-up circuit becomes "L", and then the "L" state is maintained. . Therefore, after this, the voltage level of the signal input terminal depends only on the voltage of the signal line.

[0008]

1 and 2 show an embodiment of the present invention.

FIG. 1A is a diagram showing a signal input circuit of a data bus line, and FIGS. 1B and 1C are diagrams showing a signal state at each point in the circuit.

The plurality of signal lines D _{0 to} D _n are pulled up by pull-up resistors R, respectively. Each signal line D ₀ ~
Each D _n is connected to the signal input terminal 3 via the OR circuit 4. The signal input terminal 3 outputs the data content of each of the signal lines D _{0 to} D _n . Here, the data content output from the signal input terminal 3 is D ₀ ′ to D _n ′. Each OR
The output of the latch-up circuit 1 is connected to the other terminal of the circuit 4. The latch-up circuit 1 shapes the output using the time constant of the resistor Rr and the capacitance Cr by the Schmitt buffer 5, and inputs the output to the CLR of the D flip-flop 6 having the clear terminal CLR. When the input of CLR is "L", this D flip-flop 6 sets the output of the output terminal * Q (indicated by bar Q in the figure) to "H" regardless of other inputs. On the other hand, when the input of CLR is "H", the input of the data terminal D is held when the clock terminal CK rises, and when the input of D is "H", the * Q output is set to "H". In this embodiment, since Vcc is connected to D, the first C after CLR becomes "H".
The * Q output becomes "L" at the rising edge of K, and thereafter the "L" state is maintained. On the other hand, the output of the detection means 2 is input to the CK via the AND circuit 8 and the delay circuit 9. The detection means has an n-input AND circuit 7.
The signal lines D _{0 to} D _n are connected to the input terminals of the AND circuit 7. Further, the output of the AND circuit 7 is input to the AND circuit 8. The output of the Schmitt buffer 5 of the latch-up circuit 1 is input to the other input terminal of the AND circuit 8. Further, the output of the AND circuit 8 is D
It is input to CK via the elay circuit 9.

The operation of this circuit when the power is turned on will be described.
Immediately after turning on the power, Rr / Cr / Schmidt buffer 5
Since the signal generated by (the signal at the point A) remains "L", the signal at the point A is connected to the C of the D flip-flop 6.
By inputting to LR, the output * Q (signal at point C: latch-up circuit) of the D flip-flop 6 becomes "H", and D ₀ ′ to D _n ′ (signal input terminal 3 via the OR circuit 4). ), All output levels become "H". That is, the data buses D ₀ ′ to D _n ′ can be set to “H” immediately after the power is turned on. After that, when the signal at the point A and the signals at D _{0 to} D _n all become “H”, the signal at the point C becomes “L”.
As a result, thereafter, the signal levels of D _{0 to} D _{n become} the signal levels of D ₀ ′ to D _n ′ (signal input terminal 3) as they are.

A specific example of the signal state will be described with reference to FIGS. 1 (B) and 1 (C). Rr, Cr, time T until time Tr until the output of the circuit with a Schmitt buffer 5 (signal at the point A) becomes "H", the output of the signal lines D ₀ to D _n is all "H" A case where Tr <T will be described with reference to FIG. 1B. First, the output at point C for the signal at the point A (input CLR) is "L" becomes "H", the signal lines D ₀ to D _n is "L" is a also a signal input terminal 3 (D ₀ '~D _n') becomes "H". The "H" state is maintained as it is even if the signal at the point A becomes "H". The signal at the point A is also input to the AND circuit 8, but the signal at the point B (input of CK) remains "L" because the output of the detecting means 2 becomes "L" until time T. After that, when the signal lines D _{0 to} D _n become all “H” at time T, the output of the AND circuit 8 becomes “H”, and D
The signal at the point B becomes "H" by the delay circuit 9 with a little delay, and CK rises. As a result, the signal at the point C becomes "L". After that, for example, even when a rising signal is input to CK, the input at D is "H". To be maintained. Therefore, after this, it operates as a normal data bus.

As shown in FIG. 1C, when T <Tr, the signal at the point A is in the "L" state even if D _{0 to} D _n are all "H". It remains as it is (the signal at point C is "H"). When the signal at the point A changes to "H", CLR becomes "H", and the delay circuit 9 inputs the rising signal to CK with a slight delay.

As a result, the output of the latch-up circuit becomes "L". That is, the delay circuit 9 is for ensuring the time (setup time) from when the level at the point A becomes “H” at the time of Tr to when the level at the point B changes from “L” to “H”.

FIG. 2A shows a data latch signal input circuit. Although the basic configuration is the same as that of the data bus of FIG. 1A, the purpose here is to fix the input level of the clock terminal CK of the flip-flop to "H" for a certain time when the power is turned on. In the figure, the same parts as those in FIGS. 1A and 4A are indicated by the same numbers. In this configuration, as in the case of FIG. 1A, the level at the point C becomes "H" immediately after the power is turned on, so that the level of the clock input (point D = signal input terminal) of the flip-flop is also " It becomes "H", and thereafter, this state is maintained until the levels at points Da, CK, and A are secured. Then, after the level at the three points is fixed to "H" and the level at the point C drops to "L", the flip-flop can be operated normally. Figure 2
(B) and (C) show the state.

According to the embodiment of the data latch circuit shown in FIG. 2 described above, when there are many flip-flops sharing one same clock signal or preset (reset) signal, one initialization circuit is used. Since it can be shared by all of these flip-flops, the size of the LSI chip does not change much even if this signal input circuit is incorporated in a large-scale integrated circuit, and rather the resistor used to generate the preset (reset) signal for the entire circuit Since the values of Rr and the capacity Cr can be reduced, there is a possibility that the cost can be reduced.

[0017]

As described above, according to the present invention, the voltage level immediately after power-on, which tends to become unstable, is "H".
It can be fixed to the state, and the occurrence of malfunction can be prevented.

[Brief description of drawings]

FIG. 1A is a configuration example of a signal input circuit of a data bus line according to an embodiment of the present invention, and FIGS. 1B and 1C are diagrams showing signal states at respective points in the circuit.

FIG. 2A is a configuration example of a signal input circuit of a data latch circuit according to an embodiment of the present invention, and FIGS. 2B and 2C are diagrams showing signal states of respective points in the circuit.

FIG. 3A is a diagram showing a configuration example of a conventional voltage level setting circuit for a data bus line, and FIG. 3B is a diagram showing a transition of the voltage level when the bus line is powered on.

4A is a configuration example of a preset circuit of a conventional dealer latch circuit, FIG. 4B is a diagram showing a transition of a preset signal level, and FIG. 4C is a diagram for explaining a problem of the circuit.

Claims (1)

[Claims] 1. A detection means for connecting a signal line and a latch-up circuit to a signal input terminal and for detecting that all the signal lines have become "H", and the detection means for the first time after the power is turned on. And a means for maintaining the "L" state by setting the output of the latch-up circuit to "L" when it is detected that all the lines have become "H".