JPS5824813B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a data processing device configured with a data processing circuit made up of a plurality of LSIs and the like.

FIG. 1 shows a conventional example of this type of data processing device, which is constructed from two data processing circuits LSI5 and LSI6.

3, the LSI 5 has a built-in register set circuit 10, registers 11, 12, and 13, a register selection circuit 20, and a drive circuit 21, and register selection information on the register selection control line 2 is pig-coded by the register set circuit 10. The data on input data bus 1 is transferred to registers 11 to 13.
The register selection circuit 20 selects one of the registers 11 to 13 based on the information on the register selection control line 2, and outputs the contents to the data output bus 3 via the drive circuit 21.

On the other hand, the LSI 6 has a register set circuit 10 and a register 1.
4. Built-in register selection circuit 20 and drive circuit 21, and data in registers 11 and 12 of LSI 5 are also connected to signal line 11.
0 and 120, and read and write data in the same way as LSI5.

In this way, in the configuration shown in FIG. 1, the contents of the data registers used in multiple data processing circuits are supplied from one data processing circuit to the other data processing circuit via the signal line, so the commonly used data register The more bits there are, the more likely it is that pin neck will occur.

As a way to solve this problem, as shown in Fig. 2, data registers 11 and 12 are additionally built into the LSI 5, and the LSI shown in Fig. 1 is
There is a configuration in which the signal lines 110 and 120 from SI5 to LSI6 are eliminated, and register IL12 is updated or read by LSI5 and LSI6 at the same time.

However, in Figure 2, LSI5 and LSI6 have the same register 1.
1.12, conventionally there was no means to check whether the contents matched or not, and the consistency of the data was not necessarily guaranteed.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems and to provide a means for checking whether the contents of data processing circuits outputting the same contents match.

The present invention is characterized by having an output drive circuit inside a plurality of data processing circuits that output the same content, and by incorporating a comparison circuit that compares the input and output of the output drive circuit. The purpose of this method is to check whether the contents match without having any other circuit for comparison.

Next, one embodiment of the present invention will be described in detail using the drawings.

FIG. 3 shows an embodiment of the present invention, in which LSI5 and LS shown in FIG.
I6, the input signal 50 of the output drive circuit 21
A comparison circuit 30 is added to compare the output signal 60, that is, the signal on the output bus 3 common to LSI 5 and LSI 6, and a selection circuit 31 is added to select the output 51 of the comparison circuit 30 by the signal on the signal line 2. The output side of 31 is LSI5.
The configuration is such that it is connected to a comparison error signal line 41 common to the LSI 6.

The operation of FIG. 3 is as follows.

When reading data from register 11 or register 12 in LSI 5 and LSI 6, input signal 50 of drive circuit 21
The comparison circuit 30 compares the output signal 60 of the drive circuit 21, that is, the contents of the output data bus 3, and the comparison result signal 51 is sent to the register in the own LSI by the register selection signal line 2 and the selection circuit 31. A comparison result signal is output to the comparison error signal 4 only when selected.

For example, if register 11 in LSI 5 is (1010) 2 and register 11 in LSI 6 is (1000) 2, when reading register 11°, the contents of output data bus 3 will be the same as the outputs of LSI 5 and LSI 6. The logical sum is (1010) and becomes 2.

At this time, since the input signal 50 of the drive circuit 30 in the LSI 6 is (1000)2, a mismatch occurs with the output signal 60, that is, the contents of the output data bus 3, and a comparison error occurs via the comparison circuit 30 and selection circuit 31. An error signal is output to the signal line 4, and it is detected that the contents of the same data register 111 in the LSI 5 and LSIB do not match.

Similarly, a comparison check is performed on the registers 12 of LSI 5 and LSI The LSI 5 checks the register 13 within its own LSI.

At this time, since the data on the output data bus 3 is only from the LSI 5, a comparison error should not occur, but data may be spilled from other LSIs to the output/data bus 3, or from the drive circuit inside the LSI 5. 21 is out of order,
A mismatch occurs between the input signal 50 of the drive circuit 21 and the output data bus 3, and a comparison error is detected.

1. As explained above, in the present invention, by incorporating comparison circuits in a plurality of LSIs that output the same content, content matching can be checked without having any other comparison circuit.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing a conventional example of a data processing device comprising a plurality of LSIs, etc., and FIG. 3 is a block diagram showing an embodiment of the present invention. 1... Common input bus, 2... Register selection line, 3.
...Common output bus, 4...Comparison error signal line, 5, 6
...LSI, 10...Register set circuit, 11-
14... Data register, 20... Register selection circuit, 21... Drive circuit, 30... Comparison circuit, 31...
...Selection circuit, 101, 102...LSI, 105.
...Arithmetic unit, 109...Comparison error signal line, 104.
··Signal line.

Claims (1)

[Claims] 1 Consisting of a plurality of data processing circuits each connected to a common data input bus, a common data output bus, and a common register selection control line, each of these data processing circuits is connected to the data input bus. a plurality of data registers, a selection circuit that selects the contents of any of these data registers by a signal from the register selection control line, a drive circuit that transfers an output signal of the circuit to the common data output bus; It has a comparison circuit that compares the input and output of the drive circuit, the function of the comparison circuit is enabled by a signal on the register selection control line, and the output of the comparison circuit is connected to a common comparison error signal line, A data processing device characterized in that a signal on the register selection control line simultaneously enables the functions of the selection circuits in each of the data processing circuits.