JPH05241868A - Testing system of memory error correction/detection circuit - Google Patents

Abstract

PURPOSE:To make it possible to reduce the number of input terminals by unnecessitating the exclusive data line for check bit data by writing check bit data in a memory by using a data line. CONSTITUTION:Input/output buffers 3, 4 receive the low-order half data DL of data and divides the data into either one by a selector signal. An input/output buffer 6 receives the high-order half data DH of data, the input/output thereof is connected commonly to the output of the input/output buffer 4 and is controlled by a test signal. An input/output buffer 10 receives the high-order half data DH of data, fetches the part thereof and is controlled by the test signal. In a memory 1, an ECC circuit 2 and a data line are connected, and the reading and writing in at least two kinds of data width where the input/output buffer 10 and an error bit line are connected becomes possible. When a memory 1 is used in a short data width, a check bit is transmitted from the high-order half data DH of data and is enabled to be inputted/outputted via the input/ output buffer 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory error correction / detection circuit test system for testing the normality of the operation of a memory error correction / detection circuit (hereinafter referred to as an ECC circuit).

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a configuration example of a conventional system. In the figure, 1 is a memory capable of reading and writing with at least two types of data widths. The memory 1 has a structure as shown in FIG. 5, for example. The memory shown has a 16-bit width configuration of D0 to D15. The address designation of this memory is performed every 8 bits, and the address 0 (# 0) is assigned to the first 8 bits D0 to D7 and the next 8 bits D8 to
Address 1 (# 1) is assigned to D15.

When the data unit (data width) is treated as an 8-bit structure, the addresses are # 0, # 1, # 2 ...
Thus, the memory 1 here can be used even if the unit of data (data width) is 16 bits. In this case, the address designation is increased as # 0, # 2, # 4 ....

Reference numeral 2 denotes an ECC circuit which can determine whether or not the data has been normally written in the memory 1 and can correct it when an error occurs. Reference numeral 3 denotes an input / output buffer connected to the lower half of the data bus DB00 to DB07, and 4 also denotes lower half of the data bus DB00 to DB0.
It is an input / output buffer connected to 7. The switching control of these input / output buffers 3 and 4 is performed by the data of the least significant bus AB00 of the address bus and its inverted signal (output of the inverter 5).

EC on the other side of the input / output buffers 3 and 4
It is connected to the C circuit 2. The reason why the two input / output buffers 3 and 4 are provided is that data must be written to the memory 1 in a time division manner when 16-bit data is handled by the 8-bit data bus. That is,
When AB00 is "0", the input / output buffer 3 is selected to capture lower 8-bit data, and when AB00 is "1", the input / output buffer 4 is selected and upper 8 bits are selected.
Capture bit data. As a result, 16-bit data is input to the ECC circuit 2 in a time division manner.

Reference numeral 6 denotes an input / output buffer connected to the upper 8 bits DB08 to DB15 when the data width is designated as 16 bits (word). When a word is designated, the word access signal activates the input / output buffer 6. Therefore, when a word is specified, the lower 8 bits from the input / output buffer 3
The upper 8 bits of the bits are selected from the input / output buffer 6 and enter the ECC circuit 2.

7 is a through data CH for check bit
It is an input / output buffer connected to 6 bits of B0 to CHB5. The input / output buffer 7 is controlled by the ECC through mode designating signal. That is, when the ECCTH mode designation signal is "1", the input / output buffer 7 becomes active and passes the check bits CHB0 to CHB5. This ECCTH mode designation signal is also input to the ECC circuit 2. When the ECCTH mode signal becomes "1", the check bit CB from the inside of the ECC circuit 2
The outputs of 0 to CB5 are prohibited. As a result, the bits that have passed through the input / output buffer 7 are written in the memory 1.

The ECC circuit 2 has a lower 8-bit terminal MD00.
~ MD07 is connected to the memory 1 and the upper 8 bits MD0
8 to MD15 are connected to the memory 1. Furthermore, EC
Check bits CB0 to CB5 created inside the C circuit
Are connected to the memory 1. As described above, the output of the input / output buffer 7 is also commonly connected to this check bit line. The operation of the system configured as described above will be described below. (Normal memory read / write operation) When the data line is 8 bits, the input / output buffers 3 and 4 are separated by the AB00 signal and used. That is, the lower 8-bit data is AB00.
ECC circuit 2 through input / output buffer 3 when = "0"
The upper 8-bit data is input to the ECC circuit 2 via the input / output buffer 4 when AB00 = “1”.
When the data line is 16 bits, the lower 8 bits are input to the ECC circuit 2 via the input / output buffer 3, and the input / output buffer 6 activated by the word access signal.
Then, the upper 8 bits are input to the ECC circuit 2.

When the ECC circuit 2 receives these data,
Check bits CB0 to CB5 are created internally, and the check bits CB0 to CB5 are written in the memory 1 from the respective data lines together with the received data. At this time, the number of data bits of the memory 1 is 22 bits including the check bits.

When reading the data written in the memory 1, the ECC circuit 2 also reads the check bits, examines the check bits using a predetermined algorithm, and checks whether there is a memory read error.

When there is no error, the data read from the memory 1 is output by time division using the input / output buffers 3 and 4, or when the word is designated, 16 bit data is output from the input / output buffers 3 and 6. ..

Next, consider the case where there is an error.
When there is a 1-bit error, the error position is known and error correction is performed. In the case of a 2-bit error, the error cannot be corrected, but an error signal indicating that there is an error is output. (Operation During Testing of ECC Circuit) When testing the normality of the ECC circuit 2, the ECC through mode is set. Therefore, the ECCTH mode designation signal is set to "1". As a result, output of the check bits CB0 to CB5 of the ECC circuit 2 is prohibited. Instead, the input / output buffer 7 becomes active, and the check bit data is fetched from the outside, given to the memory 1, and written. On the other hand, as described above, normal data passes through different routes between the 8-bit data line and the 16-bit data line, and
Enter the CC circuit 2 and output from the ECC circuit 2 to the memory 1
Written in.

When reading the data written in the memory 1, the ECCTH mode designation is canceled. As a result, the data read from the memory 1 and the check bit data are taken into the ECC circuit 2. Here, it is assumed that check bit data that causes a memory error is written in the memory 1 in the through mode in advance. ECC circuit 2
If the operation is normal, the ECC circuit 2 detects a memory error by a certain algorithm and outputs an error signal. If the error signal is not output even though the check bit is written so as to cause a memory error, the ECC circuit 2 has an abnormality. In this way, the normality of the ECC circuit 2 can be tested.

[0014]

In the above-mentioned conventional circuit, the interface circuit for the check bit is necessary, and it becomes difficult to provide this input / output signal line for exclusive use as the data width of the memory increases. There is. That is, when a plurality of sets of the circuit shown in FIG. 4 are provided on one printed board, the number of terminals of the connector becomes insufficient. Therefore, it becomes difficult to provide a 6-bit check bit line as shown in FIG. The data line itself requires at least 8 bits, and this data line cannot be reduced. Therefore,
The increase of check bit lines becomes a problem.

The present invention has been made in view of the above problems, and an object thereof is to provide a test system for a memory error correction / detection circuit which can reduce the number of input / output terminals.

[0016]

FIG. 1 is a block diagram showing the principle of the present invention. The same parts as those in FIG. 4 are designated by the same reference numerals. In the figure, 3 and 4 receive the lower half data DL of the data, and the first and second input / output buffers that divide the data into either one by the select signal, and 6 receive the upper half data DH of the data, the input / output of which is the above-mentioned. The third input / output buffer 10, which is commonly connected to the output of the second input / output buffer 4 and is controlled by the test signal, receives the upper half data DH of the data, takes in a part of the data DH, and controls it by the test signal. This is a fourth input / output buffer that is

An EC 2 is connected to the first and second input / output buffers 3 and 4 and performs memory error correction / detection.
A C circuit 1 is a memory which is connected to the ECC circuit 2 and a data line and is connected to the fourth input / output buffer 10 and an error check bit line, and which is capable of reading and writing with at least two kinds of data widths. ..

[0018]

When the memory 1 is used with a short data width, a check bit is sent from the upper half data DH of the data so that the check bit can be input to and output from the memory 1 via the fourth input / output buffer 10. This eliminates the need for a data line dedicated to the check bit, and reduces the number of input / output terminals.

[0019]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 2 is a configuration block diagram showing an embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. In the figure, 3 and 4 are the lower half data D of the data
First and second input / output buffers which receive H (B00 to DB07) and are separated into one by a select signal, and 6 are upper half data (DB08 to DB1)
5), and its input / output is the second input / output buffer 4
Third output commonly connected to and controlled by a test signal
The input / output buffer 10 is a fourth input / output buffer which receives the upper half data DH of the above data, takes in a part of it (6 bits of DB08 to DB13), and is controlled by the test signal.

The address signal AB00 enters the second input / output buffer 4, and its inverted signal enters the input / output buffer 3 from the inverter 3a.

An EC 2 is connected to the first and second input / output buffers 3 and 4 and performs memory error correction / detection.
A C circuit 1 is a memory which is connected to the ECC circuit 2 and a data line and is connected to the fourth input / output buffer 10 and an error check bit line, and which is capable of reading and writing with at least two kinds of data widths. ..

Reference numeral 10a is an AND gate for receiving the ECCTH mode signal and the unit test mode signal, and 10b is an inverter for inverting the unit mode signal. AND gate 10a
Is output to the fourth input / output buffer 10.
11 is a check bit register (hereinafter referred to as CB register) that holds 6 check bits, and 11a is an EC
An AND gate that receives the CTH mode designation signal and the inverted signal of the unit test mode signal, and 11b is a three-state buffer that receives the output of the CB register 11. The output of the AND gate 11a is input as a control signal for the buffer 11b. Explaining the operation of the circuit configured in this way,
It is as follows.

The normal read / write operation of the memory 1 is similar to that of the conventional circuit shown in FIG. That is, the 16-bit data of the input / output buffers 3 and 4 (or 6) enters the ECC circuit 2, and the check bit 6 bits are added to this,
Written to memory 1. ECC when reading memory
The circuit 2 checks whether or not there is a memory error based on the read check bit. If there is a memory error, it is corrected if it can be corrected, and an error signal is output even if it cannot be corrected.

Next, the operation of the ECC circuit 2 during the test will be described. (1) When testing as a single memory card At this time, the ECCTH mode designation and the single test mode are set by the ECCTH mode signal and the single test mode signal. At this time, each mode signal becomes "1".
As a result, the output of the AND gate 10a becomes "1" and activates the fourth input / output buffer 10. At this time,
The output of the AND gate 11a becomes "0", and the 3-state buffer 11b is set to high impedance to prohibit the output of the CB register 11. The ECCTH mode signal enters the ECC circuit 2 and the internal check bit C
The output of B0 to CB5 is prohibited.

In this state, the memory tester (not shown) sends test data to DB00 to DB07 and DB08 to DB07.
A check bit is added to 13 and output. DB00-D
The test data from B07 passes through the input / output buffer 3 to E
Enter the CC circuit 2. Then, MD00 of the ECC circuit 2
It is output from MD07 and enters the memory 1.

On the other hand, the check bits input from DB08 to DB13 directly enter the memory 1 via the input / output buffer 10. Then, it is written in the memory 1 as data of 8 bits + 6 bits.

After writing the data and the check bit in the memory 1, the ECCTH and the unit test mode are released. As a result, these mode signals become "0". EC
When the CTH mode signal becomes "0", the operation of the internal check bit of the ECC circuit 2 becomes possible. Also at this time, C
The output of the B register 11 remains prohibited.

In this state, the data is read from the memory 1 and taken into the ECC circuit 2. At this time, since the check bit terminals CB0 to CB5 of the ECC circuit 2 are active, the check bits read from the memory 1 are also fetched into the ECC circuit 2. And the ECC circuit 2
Performs error check on the imported data.

Here, if error data is given to the check bits given from DB08 to DB13 in advance, EC
When the operation of the C circuit 2 is normal, the ECC circuit 2 outputs an error signal. This makes it possible to determine the normality of the ECC circuit. Further, according to the present invention, since the check bit is provided by using the data lines DB08 to DB13, it is not necessary to newly provide a data line dedicated to the check bit. (2) When a test is performed on the system In this case, check bit data is written in the CB register 11 in advance. Then, data is written by designating only the ECCTH mode. Since only the ECCTH mode signal is "1", the output of the AND gate 10a becomes "0" and the fourth input / output buffer 10 is disconnected. On the other hand, the AND gate 11a becomes "1",
The 3-state buffer 11b becomes active. Therefore, the output of the CB register 11 is written to the memory 1 in addition to the data from DB00 to DB07.

At the time of reading, if the ECCTH mode is released and the contents of the memory 1 are read and loaded into the ECC circuit 2, the normality test can be performed. In this case,
If the check bit data is written in the CB register 11 from the data line, the ECC circuit can be tested as a system, not from the memory tester.

FIG. 3 is a diagram showing a detailed configuration example of the embodiment of the present invention, showing the configuration of the input stage of the ECC circuit. The same parts as those in FIG. 2 are designated by the same reference numerals. In the figure,
Reference numeral 20 is a gate circuit for various control signals (AB00, word access designation signal, memory read designation signal, ECC
In response to the through mode designating signal and the unit test mode designating signal), the control signals of the respective input / output buffers 3, 4, 6, 10 are output. The corresponding numbers from the figure are connected to each other. The function of the control signal is the same as that of the embodiment shown in FIG.

The CB register 11 has DB00 to DB07.
6 bits of the data are stored in the CB register 11, and the check bit data is placed on the data line and latched in the CB register 11 during the system test. With such a configuration, the check bit data can be arbitrarily set from the system side.

[0034]

As described above in detail, according to the present invention, since the check bit data is written in the memory by using the data line, the dedicated data line for the check bit data is unnecessary. Therefore, the number of input / output terminals can be reduced.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a configuration block diagram showing an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a detailed configuration example of an embodiment of the present invention.

FIG. 4 is a diagram showing a configuration example of a conventional system.

FIG. 5 is a diagram showing a configuration example of a memory.

[Explanation of symbols]

 1 memory 2 ECC circuit 3, 4, 6, 10 input / output buffer

Claims (2)

[Claims] 1. The first and second input / output buffers (3) and (4) for receiving the lower half data DL of the data and dividing into either one by a select signal, and the upper half data DH of the data, and A third input / output buffer (6) whose input / output is commonly connected to the output of the second input / output buffer (4) and controlled by a test signal
A fourth input / output buffer (10) which receives the upper half data DH of the data and fetches a part of the data DH and is controlled by the test signal; and the first and second input / output buffers (3), An ECC circuit (2) connected to (4) for memory error correction / detection, the ECC circuit (2) is connected to a data line, and the fourth input / output buffer (10) and an error check bit are connected. A memory (1) capable of reading and writing with at least two kinds of data widths to which lines are connected, and when the memory (1) is used with a short data width, an error is caused by using unused data bits. A test system for a memory error correction / detection circuit, characterized in that check bits can be input / output via a fourth input / output buffer (10). 2. A check bit register (11) capable of arbitrarily generating a check bit of an ECC circuit (2) is provided so that a check bit of arbitrary data can be written in a memory (1). Claim 1
Test system for the described memory error correction / detection circuit.