JP2605062Y2 - Bidirectional balanced transmission circuit - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-way balanced transmission circuit in which a driver and a receiver having an emitter-coupled logic (ECL) configuration are connected to a balanced transmission line and a large noise margin can be obtained.

[0002]

2. Description of the Related Art Conventionally, in an IC test system and other computer systems, for example, data is exchanged between a plurality of modules mounted in a slot provided in a system bus of a tester main body.

FIG. 3 shows an example of a transmission circuit in which a plurality of modules are connected to a bus. In the figure,
A transmission line (only one line is shown) 51 is terminated at both ends,
A plurality of modules M (1), M (2),
.., M (k) are connected. A bidirectional interface circuit 52 composed of a driver 53 and a receiver 54 is connected to these modules. In a system that requires high speed, such as an IC test system, the interface circuit is configured by ECL.

FIGS. 4 and 5 show examples of a conventional connection between a module having a bidirectional interface circuit using ECL and a bus. 4, a driver 63 and a receiver 6 constituting an interface circuit 62 are shown.
Numerals 4 each include a NOR gate. In the figure, the driver 63 is wired-OR connected to the transmission line, and both ends of the transmission line (in this case, the bus) are terminated by a resistor _RT having a resistance value substantially equal to the line impedance. A bias V _TT for driving the driver 63 is applied to a terminal of the terminating resistor _RT that is not connected to the bus 61, and the output voltage of the driver 63 is pulled down by the bias.

In FIG. 5, a driver 73 constituting an interface circuit 72 is provided by a NOR gate.
Similarly, the receiver 74 is constituted by a differential signal input receiver. Also in this case, all the drivers 73 are wired OR-connected to the transmission path (in this case, the twisted pair cable 71), and both ends of the twisted pair cable 71 are terminated by the resistor RT. The emitter voltage VEE is connected to the driver 73 of the resistor RT via the resistor r.
, And the base voltage VBB is applied to the receiver 74 side of the resistor RT. Also in this case, the resistance r
And the terminating resistor RT is used as a pull-down resistor for the output voltage of the driver 73, and the output voltage is the resistor r
And the potential is lowered to a predetermined potential via the terminating resistor RT.

However, all of the above transmission lines are unbalanced, and when the frequency of the transmission line is high (for example, 50
MHz or more), line length, stub, IC
Transmission errors may occur due to the effects of loads and the like.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a bidirectional balanced transmission circuit having a large noise margin, in which an interface circuit including a driver and a receiver having an ECL structure is connected to a balanced transmission line.

[0008]

[Outline of the Invention] The balanced transmission circuit of the present invention has a line at both ends.
Has a resistance value approximately equal to the
Terminated by a load resistor biased at a predetermined potential
The balanced transmission line has an emitter-coupled logic configuration,
Driver with two output terminals and receiver with two input terminals
Of the interface circuit consisting of
OR connection, and each of the interface circuits is
Control to enable or disable the driver
Each has a signal input terminal.
H output from one output terminal of the driver
Bell voltage is output to one line of the balanced transmission line,
From the other output terminal of the driver, the L level voltage is
Output to the other line of the balanced transmission line, and the control signal
Drivers disabled by both output terminals
Output the L level voltage on both lines of the balanced transmission line.
Operable to operate.

In the present invention, the driver is constituted by a differential signal output driver and a pair of AND gates, and the receiver is constituted by a differential signal input receiver. Each of the differential signal output terminals is connected to one input terminal of each AND gate, the other input terminal of each AND gate is the control signal input terminal, and the output terminal of each AND gate is connected to a balanced transmission line. It is also characterized by being connected.

The balanced transmission line in the present invention may be a bus or a twisted pair cable as long as it is a so-called party line. It is desirable that the value of the line impedance of the balanced transmission line and the value of the load resistance at the end of the balanced transmission line are the same, but the case where the transmission impedance changes due to the circuit connected on the transmission line and the influence of the stub are ignored. In the case where it becomes impossible, it is preferable to adjust the load resistance value. Usually, a control circuit for enabling or disabling the output of the receiver is provided in the output stage of the receiver.

The basic operation of the balanced transmission circuit according to the present invention will be described below. First, a driver of an interface circuit (here, referred to as an interface circuit A for convenience) is enabled, and an interface circuit other than the interface circuit A (here, an interface circuit A for convenience) is enabled.
Receiver output over the face referred to as circuit B) is assumed to become enabled. At this time, the driver of the other interface circuits other than interface circuit A to be disabled, and all receiver outputs other in <br/> te face circuits other than the interface circuit B is a disabled state.

[0012] In ECL, can be wired-OR connected to the direct transmission path driver, when outputting the driver interns face circuit A is "1", two of the wires H level of the balanced transmission line The voltage and the L level voltage will appear. Further, even when the output driver is "0" interns face circuit A, the two wires of the balanced transmission line, L-level voltage in the opposite polarity to the case of outputting the above-described driver "1" And the H level voltage will appear.

Since the receiver of the ECL configuration has a high input impedance, the DC current is biased on the two wires of the balanced transmission line at a predetermined voltage (a voltage lower than the H level and the L level). And the AC current flows in opposite phases on the two wires of the balanced transmission line.

[0014] The direct current, looking viewed from the driver of the interface circuit A, since a state in which half of the terminating resistors of the two load resistance _{Z 0 (Z} 0/2) are connected in parallel, two _{Z 0} / 2 parallel connections _(Z 0/4) is to act as a pull-down resistor.

Further, the alternating current, the impedance seen by the driver of the interface circuit A, the parallel connection of the two terminating resistors Z _0. The receiver of the interface circuit B outputs an H or L level voltage according to a differential signal appearing on the two wires of the balanced transmission path.

In the conventional transmission line, unbalanced transmission is performed. On the receiver side, an H or L level voltage is recognized based on a difference from a threshold voltage. On the other hand, in the transmission line of the present invention, balanced transmission is performed. H or L of driver
From the level voltage difference, the H or L level voltage on the receiver side is recognized. Thus, according to the transmission line of the present invention, a wider noise margin can be obtained as compared with the conventional transmission line.

[0017]

FIG. 1 is a circuit diagram showing an embodiment of a balanced transmission circuit according to the present invention. In the figure, modules M (1) to M (k) are connected to a balanced transmission line (a bus in this case) via an interface circuit 2. In FIG. 1, only one bus line (configured by a pair of wires 1a and 1b) 1 is shown.

The opposite ends line impedance _{Z 0} is the bus line 1 (in the drawing, 200 [Omega) is terminated by a _R T resistor having the same value (indicated by a series connection of two _Z 0/2 (= 100 [Omega)) ing. Midpoint of the R _{T (i.e., Z} 0/2 connection points) is biased by the output voltage a lower voltage _{V TT} than the later-described driver 3. Thus, the terminating resistor _RT also plays a role as a pull-down resistor of the driver 3 (the output terminal has an open emitter configuration).

Each interface circuit 2 includes a driver 3 having an ECL configuration and a receiver 4. The driver 3 includes a differential signal output driver 31 and a pair of ANs.
D-gates 32a and 32b, and differential output terminals of the differential signal output driver 31 are AND gates 32a and 32b.
Are connected to one input terminal. The other input terminal of each of the AND gates 32a and 32b is a control signal input terminal. An H level signal is input as an enable signal and an L level signal is input as a disable signal.

The ECL used in FIG. 1 (specifically,
In a 10KH series manufactured by Motorola, USA, the logic level is such that the L level output voltage is -1.75 V as a standard and the H level output voltage is -0.9 V as a standard with respect to the ground level. V _TT supplied to the middle point of the terminating resistor _RT is -2.0V.

Hereinafter, the operation of the transmission circuit of FIG. 1 will be described.
Enable signal (H level signal in this case) to driver 2 of interface circuit 1 of module M (1)
Is entered. Although not shown,
A selection circuit for enabling and disabling the receiver 4 is provided at a stage subsequent to the differential signal input driver 31, and the selection circuit for enabling the output of the receiver 4 of the interface circuit 2 of the module M (2) is enabled. I do.

In this case, the modules M (2), M
(3), the driver 3 of the interface circuit 2 and the modules M (1), M (3), M (4),
, The outputs of the receivers 4 of the interface circuit 2 are disabled. Regardless of whether the driver 3 of M (1) outputs “1” or “0”, one of the two wires of the bus line 1 has an H level and the other has an L level. Is output.

Further, other than the M (1) which is a rice Buru driver 3 operates with two terminals to output the L level. For example, when the driver 3 of M (1) is outputting "1", the wire (1
The emitter potential of the output stage transistor of the driver other than M (1) connected to a) becomes the same potential as the wire. When the driver 3 of M (1) is outputting "1", the emitter potential of the output stage transistor of the driver 3 other than M (1) connected to the wire (1b) at L level. Is L level because the driver 3 originally outputs L level. In addition,
When the driver 3 of M (1) outputs “0”, the L level is output to one wire (1b) and the H level is output to the other wire (1a). Compared to the case where the driver 3 outputs "1", only the wires 1a and 1b are replaced.

As shown in FIG. 2, when the bus line 1 is viewed DC from the connection point of M (1) (DC currents flowing through the two wires are indicated by i _dc and i ′ _dc ), the terminal Z _0/2
Are present at both ends. Therefore, a state where Z _0/4 (2 one parallel connection circuit of the Z _0/2) is connected to the output terminal of the driver 3. Therefore, this Z _0/4 (= 50
Ω) functions as a pull-down resistor of the driver 3. When viewed in terms of alternating current (in FIG. 2, the AC currents flowing through the two wires are indicated by i _ac and −i _ac ), Z ₀ exists at both ends of the bus line 1 as shown in FIG. it means that, so that the line impedance Z ₀ and the impedance-matched.

[0025]

As described above, in the conventional ECL, the interface circuit which could not be "balanced" in the case of bidirectional communication is constituted by the balanced transmission line in the present invention, so that the noise margin of the conventional ECL is almost twice that of the conventional one. A data transmission circuit can be realized.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a basic embodiment of the present invention.

FIG. 2 is a diagram showing how DC current and AC current flow in the circuit of FIG. 1;

FIG. 3 is a basic configuration diagram of a conventional transmission circuit in which a plurality of modules are connected to a bus.

FIG. 4 is a diagram showing a conventional transmission circuit when a transmission path is a bus BUS.

FIG. 5 is a diagram illustrating a conventional transmission circuit when a transmission path is a twisted pair cable.

[Explanation of symbols]

 Reference Signs List 1 bus line 1a, 1b bus line wire 2 bidirectional interface circuit 3 driver 31 differential signal output driver 32a, 32b AND gate 4 receiver

Claims (2)

(57) [Scope of request for utility model registration] 1. Both ends,Almost equal to line impedance
Has a new resistance valueAnd the midpoint is biased at a predetermined potential.
WhatThe transmission line terminated by a load
Coupled logic configurationWith two output terminalsdriver
WhenHas two input terminalsReceiverWhenInterface consisting of
Of multiple balanced circuits connected by wired OR
A transmission circuit, wherein each of the interface circuits enables a driver
Or the control signal input terminal to be disabled
Have, One of the drivers enabled by the control signal
From the output terminal of the balanced transmission line
Is output to one line and is
Have the L level voltage applied to the other line of the balanced transmission line.
Output A driver disabled by the control signal
Converts the L level voltage from both output terminals to the balanced transmission path.
Work to output on both tracks,  A bidirectional balanced transmission circuit, characterized in that: 2. The driver comprises a differential signal output driver and a pair of AND gates, and the receiver comprises a differential signal input receiver, wherein the differential signal output driver outputs a differential signal. Each of the terminals is connected to one input terminal of each AND gate, the other input terminal of each AND gate is used as the control signal input terminal, and the output terminal of each AND gate is connected to a balanced transmission line. The bidirectional balanced transmission circuit according to claim 1, wherein: