CN112118002A

CN112118002A - Circuit for switching output logic level

Info

Publication number: CN112118002A
Application number: CN202010788889.XA
Authority: CN
Inventors: 上官宇剑
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2020-08-07
Filing date: 2020-08-07
Publication date: 2020-12-22

Abstract

The invention discloses a circuit for switching output logic level, which comprises a signal output driver, a signal receiver and a plurality of matching circuits, wherein the signal output driver is connected with the signal receiver; the signal output driver is connected with the signal receiver through a plurality of signal lines, and the outputs of different matching circuits are intersected with different signal lines; the matching circuit includes: the circuit comprises a control chip, a first short-circuit component, a second short-circuit component and a plurality of resistors, wherein the plurality of resistors are connected in series, the first short-circuit component is configured to respond to the control chip to output a first voltage to short out a first resistor in the plurality of resistors, the second short-circuit component is configured to respond to the control chip to output a second voltage to short out a second resistor in the plurality of resistors, and the output of a matching circuit is located in the resistors connected in series. The scheme of the invention controls the on-off of the MOS tube by sending different voltages, thereby controlling the output bias voltage and the equivalent terminating impedance of the output point of the resistor network to respectively meet the output requirements of LVPECL and HCSL levels, and realizing the compatibility of two standard level signals.

Description

Circuit for switching output logic level

Technical Field

The present invention relates to the field of communications, and more particularly, to a circuit for switching an output logic level.

Background

For digital communications, particularly communications between digital chips using high speed digital buses, the LVPECL level and the HCSL level are the logic levels for a number of applications. Some devices or devices can only support one of the level standards, which makes level matching between the host side and the terminal device difficult.

Disclosure of Invention

In view of this, an object of the embodiments of the present invention is to provide a circuit for switching an output logic level, in which a matching circuit is provided, and different voltages are output from the matching circuit to control on/off of an MOS transistor, so as to control an output bias voltage and an equivalent termination impedance of an output point of a resistor network to respectively meet the requirements of output levels of an LVPECL and an HCSL, thereby implementing compatibility of signals with two standard levels.

In view of the above, an aspect of the embodiments of the present invention provides a circuit for switching an output logic level, including: a signal output driver, a signal receiver, and a plurality of matching circuits;

the signal output driver is connected with the signal receiver through a plurality of signal lines, and the outputs of different matching circuits are intersected with different signal lines;

the matching circuit includes: the circuit comprises a control chip, a first short-circuit component, a second short-circuit component and a plurality of resistors, wherein the plurality of resistors are connected in series, the first short-circuit component is configured to be used for responding to the control chip to output a first voltage to short out a first resistor in the plurality of resistors, the second short-circuit component is configured to be used for responding to the control chip to output a second voltage to short out a second resistor in the plurality of resistors, and the output of the matching circuit is located in the resistors connected in series.

In some embodiments, the first shorting component comprises: the grid electrode of the first MOS tube is connected with the output of the control chip, and the source electrode of the first MOS tube is grounded; and the grid electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, and the source electrode and the drain electrode of the second MOS tube are respectively connected with two ends of the first resistor.

In some embodiments, the first shorting assembly further comprises: and one end of the first pull-up resistor is connected with the grid electrode of the first MOS tube, and the other end of the first pull-up resistor is connected with a power supply voltage.

In some embodiments, the second shorting assembly comprises: and the grid electrode of the third MOS tube is connected with the output of the control chip, and the source electrode and the drain electrode of the third MOS tube are respectively connected with two ends of the second resistor.

In some embodiments, the output of the matching circuit is located between the first resistance and the second resistance.

In some embodiments, the number of the series resistors is even, and the output of the matching circuit is led out from the connection end of the two resistors at the middle.

In some embodiments, the number of series resistors is odd, and the output of the matching circuit is taken from either end of the middle most resistor.

In some embodiments, the circuit further comprises a termination resistor, one end of the termination resistor is connected to the signal line, and the other end of the termination resistor is grounded.

In some embodiments, the resistance of the termination resistor is positively correlated with the value of the output voltage.

In some embodiments, the circuit further comprises an ac coupling capacitor disposed between the signal output driver and the signal line intersection.

The invention has the following beneficial technical effects: by arranging the matching circuit, different voltages are output in the matching circuit to control the on-off of the MOS tube, so that the output bias voltage and the equivalent terminating impedance of the output point of the control resistor network respectively meet the output requirements of LVPECL and HCSL levels, and the compatibility of two standard level signals is realized.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of a circuit for switching output logic levels according to the present invention;

fig. 2 is a schematic diagram of a matching circuit of the circuit for switching output logic levels according to the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

In view of the above object, a first aspect of an embodiment of the present invention proposes an embodiment of a circuit for switching an output logic level. Fig. 1 is a schematic diagram of an embodiment of a circuit for switching an output logic level according to the present invention, and fig. 2 is a schematic diagram of a matching circuit of the circuit for switching an output logic level according to the present invention. As shown in fig. 1 and 2, an embodiment of the present invention includes the following components:

a signal output driver 1, a signal receiver 2, and a plurality of matching circuits 3;

the signal output driver 1 and the signal receiver 2 are connected through a plurality of signal lines (a, b), and the outputs of different matching circuits 3 intersect with different signal lines;

the matching circuit 3 includes: a control chip (CPU/CPLD), a first shorting component 31, a second shorting component 32, and a plurality of resistors (R1, R2, R3, R4), the plurality of resistors being connected in series, the first shorting component 31 being configured to short a first resistor (R2) of the plurality of resistors in response to the control chip outputting a first voltage, the second shorting component 32 being configured to short a second resistor (R4) of the plurality of resistors in response to the control chip outputting a second voltage, the output of the matching circuit being located in the series of resistors.

The source end of the signal transmission circuit based on alternating current coupling is an output driver of a LVPECL (Low Voltage Positive Emitter coupled Logic) signal, the driver is integrated in a digital or analog chip using the high-speed signal, if the receiving end is also the LVPECL, according to the Voltage of a level and the impedance matching requirement, the VTT Voltage should be 2.0V, and the pull-up resistance is 50 ohm; if the level required by the receiving end is HCSL (High-speed Current Steering Logic), the VTT voltage should be 0.35V and the pull-up resistance 50ohm according to the voltage of the level and the impedance matching requirement. The high-speed signal leads out a respective terminal P and N at a location close to the signal receiver 2 for connection to the output of the matching circuit.

In some embodiments, the circuit further comprises a termination resistor, one end of the termination resistor is connected to the signal line, and the other end of the termination resistor is grounded. After the signal is output by the driving device, the two differential lines are respectively short-circuited to the ground through the terminating resistor Rp at the position close to the driving device.

In some embodiments, the resistance of the termination resistor is positively correlated with the value of the output voltage. According to different power supply voltages of the driver, different resistance values of the terminating resistor are respectively selected: vdd 3.3V, Rp 120 ohm; vdd 2.5V and Rp 60 ohm.

In some embodiments, the circuit further comprises an ac coupling capacitor 4, the ac coupling capacitor 4 being disposed between the signal output driver 1 and the intersection of the matching circuit and the signal line. After passing through the terminating resistor Rp, the output signals respectively pass through an ac coupling capacitor and then reach the receiver end through a long transmission line. The ac coupling capacitor is generally selected to be 100nF, and functions to ensure that the ac component of the transmitted high-speed signal can be smoothly transmitted to the receiving end of the backend device, and simultaneously to block the dc component in the signal from being transmitted to the other end, because the dc common mode voltages of the transmitting end and the receiving end are different.

In some embodiments, the number of the series resistors is even, and the output of the matching circuit is led out from the connection end of the two resistors at the middle. For example, a total of four resistors, from top to bottom, are R1, R2, R3 and R4, and the output of the matching circuit can be led out from the connection end of R2 and R3.

In some embodiments, the number of series resistors is odd, and the output of the matching circuit is taken from either end of the middle most resistor. For example, a total of five resistors, R1, R2, R3, R4 and R5 in this order from top to bottom, may be provided to extract the output of the matching circuit at any one of the two ends of R3.

When the GPIO pin outputs high level, the connection between the drain and the source of the first MOS transistor N1 is low level, so that the drain and the source of the second MOS transistor N2 are controlled to be disconnected, and the first resistor R2 connected with the N2 in parallel can work normally. Meanwhile, the gate input of the third MOS transistor N3 is also high, the drain is connected to the source, which is equivalent to short to ground GND, so the second resistor R4 is short-circuited and cannot operate normally.

When the GPIO pin outputs low level, the drain of the MOS transistor N1 is high level, so the drain of the control MOS transistor N2 is connected with the source, and the resistor R2 connected with the N2 in parallel is short-circuited and can not work normally. Meanwhile, the MOS transistor N3 has a low gate level input, and the drain and the source of the MOS transistor are disconnected, so that the normal operation of the resistor R4 is not affected.

Through calculation and analysis, R1 ═ 82ohm, R2 ═ 390ohm, R3 ═ 56ohm, and R4 ═ 71.5ohm, respectively, were selected. When the GPIO pin of the CPU/CPLD is at a high level, a pull-up resistor Ru at a P/N point is 472ohm, a pull-down resistor Rd is 56ohm, an equivalent termination resistor Rtt is 50ohm, and the bias voltage is 0.35V; when the GPIO pin of the CPU/CPLD is at a low level, the pull-up resistor Ru at the P/N point is 82ohm, the pull-down resistor Rd is 127.5ohm, the equivalent termination resistor Rtt is 49.9ohm, and the bias voltage is 2.01V.

Through the calculation and analysis, when the controlled GPIO signal is at low level, the whole circuit outputs a high-speed signal meeting the LVPECL requirement to the receiving end, and when the GPIO signal is at high level, the whole circuit outputs a high-speed signal meeting the HCSL requirement.

The LVPECL level signal output by the LVPECL level signal processing circuit firstly passes through the terminating resistor and the AC coupling capacitor at the source end and then is sent to the receiver at the rear end through the transmission line. Before the signal enters the receiver, it is connected to a voltage and impedance matching circuit. The voltage and impedance matching circuit mainly comprises a resistance network and a control MOS tube. The switching control GPIO sent by the CPU controls the on-off of the MOS tube, and further controls the output bias voltage and the equivalent terminating impedance of the output point of the resistor network. When the GPIO output is a default low level, the resistor network provides a termination impedance with Vtt being 2.0V bias voltage and Rtt being 49.9ohm by adjusting the effective resistance value of a pull-down resistor on an output point, so as to meet the LVPECL level output requirement; when the GPIO output is high level, the resistor network provides a termination impedance with Vtt being 0.35V bias voltage and Rtt being 50.1ohm by adjusting the effective resistance value of the pull-down resistor on the output point, so as to meet the HCSL level output requirement; thereby realizing the compatibility of two standard level signals.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A circuit for switching an output logic level, comprising:

a signal output driver, a signal receiver, and a plurality of matching circuits;

2. The circuit of claim 1, wherein the first shorting component comprises:

the grid electrode of the first MOS tube is connected with the output of the control chip, and the source electrode of the first MOS tube is grounded; and

and the grid electrode of the second MOS tube is connected with the drain electrode of the first MOS tube, and the source electrode and the drain electrode of the second MOS tube are respectively connected with two ends of the first resistor.

3. The circuit of claim 2, wherein the first shorting assembly further comprises:

and one end of the first pull-up resistor is connected with the grid electrode of the first MOS tube, and the other end of the first pull-up resistor is connected with a power supply voltage.

4. The circuit of claim 1, wherein the second shorting component comprises:

and the grid electrode of the third MOS tube is connected with the output of the control chip, and the source electrode and the drain electrode of the third MOS tube are respectively connected with two ends of the second resistor.

5. The circuit of claim 1, wherein the output of the matching circuit is located between the first resistance and the second resistance.

6. A circuit as claimed in claim 5, wherein the number of resistors in series is even, and the output of the matching circuit is taken from the connection of the two resistors at the very middle.

7. The circuit of claim 5, wherein the number of series resistors is odd, and wherein the output of the matching circuit is taken from either end of the middle most resistor.

8. The circuit of claim 1, further comprising a termination resistor, wherein one end of the termination resistor is connected to a signal line and the other end of the termination resistor is connected to ground.

9. The circuit of claim 8, wherein the resistance of the termination resistor is positively correlated to the value of the output voltage.

10. The circuit of claim 1, further comprising an ac coupling capacitor disposed between the signal output driver and the signal line intersection.