JPH1041982A - Current drive type communication circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the adverse effect due to a voltage drop in a current path by connecting a core circuit section and a bonding pad while being separated into a current path and a non-current path and providing the wiring part of the paths to an outside of the core circuit section separately. SOLUTION: A core circuit section 51 of a communication IC 12 is provided with a current buffer 42 connecting to pads TpA, TpA#, differential voltage detectors 43-45, a comparator 47 and a resistor R2. The wiring to connect the core circuit section 51 and the bonding pads is separated into a current path 61 connected from the pad Tp to the current driver 42 and a non-current path 62 connecting to the voltage detectors 43-47 from a branch point PP on the path 61. Thus, the voltage detectors connecting to the non-current path 62 can detect a voltage almost without receiving the adverse effect due to the voltage drop in the current path.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a current-driven communication circuit (integrated circuit), and more particularly to a current-driven communication circuit characterized by a wiring method inside an IC.

[0002]

2. Description of the Related Art Conventional video equipment and audio equipment are provided with input / output terminals for analog signals, and video signals and audio signals are communicated between the equipment in analog form. 2. Description of the Related Art In recent years, with the development of digital devices, digital communication has been widely used in place of analog communication in order to directly communicate signals processed in digital form. A representative standard for digital communication is defined by IEEE1394.

FIG. 1 is a diagram showing a configuration of a communication network based on the IEEE 1394 standard.

The nodes N1 and N2 are devices each having a communication interface, and are connected to each other by two sets (four) of communication cables 31 and 32. For example, the node N1 transmits packet data, and the node N2 receives the packet data. Conversely, the node N2 transmits the packet data and the node N1
Receives the packet data. Here, an example is shown in which two nodes N1 and N2 are connected, but it is also possible to connect a plurality of nodes.

The node N1 has a communication IC 12 and an external circuit 13. The communication IC 12 has five bonding pads TpBias, TpA, TpA #, TpB, T
pB #. The external circuit 13 is provided outside the communication IC 12 and is connected to five pads Tp of the communication IC 12 by leads L1 to L5. Communication cables 31 and 3
2 is connected to an external circuit 13 via a connector.

The node N2 has the same configuration as the node N1, and has a communication IC 22 and an external circuit 23. The communication IC 22 includes five bonding pads (hereinafter, referred to as pads) TpBias, TpA, TpA #, TpB, T
It is connected to an external circuit 23 via pB #. The communication cables 31 and 32 are connected to the external circuit 23.

The nodes N1 and N2 are connected to two sets of cables 31
And 32 are connected to a so-called cross. Communication I
In C12, the pads TpA and TpA # are connected to the cable 31 as a set, and the pads TpB and TpB # are connected to the cable 32 as a set. On the other hand, communication IC
At 22, the pads TpB and TpB # are connected to the cable 31 as a set, and the pads TpA and TpA # are connected to the cable 32 as a set.

FIGS. 2 and 3 show a detailed circuit configuration of the communication network of FIG. FIG. 2 shows the upper half of FIG.
FIG. 3 shows the lower half of FIG. FIGS. 2 and 3 are only left and right symmetrical with respect to the communication cables 31 and 32, and have the same circuit configuration.

At one node, pads TpB and TpB
B # is a pad for transmitting a data signal, and pads TpA and TpA # are pads for transmitting a strobe signal obtained by encoding the data signal. The circuit of FIG. 3 will be mainly described to describe the case where data signals are transmitted from pads TpB and TpB # of node N1.

In FIG. 3, the communication IC 1 of the node N1
2 is connected to a cable (twisted pair line) 32 via pads TpB and TpB #. Communication I of node N2
C22 is connected to a cable (twisted pair line) 32 via pads TpA and TpA #. Twisted pair wire
Used for general balanced differential signal transmission.

At both ends of the cable 32, a terminating resistor R1 in which two 55Ω resistors are connected in series is connected. That is, the terminating resistor R1 is connected between the pads TpB and TpB # and between the pads TpA and TpA # as external circuits.
Are connected respectively.

First, a set of pads TpA and TpA # connected to the right side of the cable 32 will be described. Communication I
C22 applies a DC bias of 1.85 V to the pad TpBia.
A buffer 41 that supplies the middle point of the terminating resistor R1 via s
And a current driver 42 for supplying a differential current to the twisted pair line, differential voltage detectors 43, 44, 45 for detecting a differential voltage of the twisted pair line, and detecting a common mode voltage of the twisted pair line. The common-mode voltage detector 46 of FIG.

The communication IC 22 roughly has two communication phases of packet data and arbitration (bus arbitration). The packet data is a binary logic of “0” or “1”. The arbitration is performed when a transmission request is made, for example, “0”, “1”, or “Z”.
Is a three-valued logic. “Z” is in a high impedance (open) state.

The differential voltage detector 43 is a packet receiver for receiving and detecting packet data. The differential voltage detector 44 is an arbitration receiver for receiving and detecting arbitrations "Z" and "0". The differential voltage detector 45 has an arbitration “Z”.
And an arbitration receiver for receiving and detecting "1".

The resistor R2 is formed by connecting two 10 kΩ resistors in series, and is connected between the pads TpA and TpA # inside the communication IC 22. The in-phase voltage detector 46 has a positive terminal connected to the middle point of the resistor R2 and a negative terminal connected to the pad TpBias (1.85 V). Since the resistor R2 has a higher resistance than the terminating resistor R1, almost no current flows. The common mode voltage detector 46 can detect the common mode voltage of the twisted pair wire. The common-mode voltage is a potential at the middle point of the resistor R2, and corresponds to a bias potential when no common-mode current flows.

The voltage detectors 44, 45 and 46 are comparators to which an offset of, for example, -82 mV has been applied. That is, in the voltage detector, the potential of the + terminal is −
When the potential of the terminal becomes lower than the potential of the terminal by 82 mV or more, a signal is output.

Next, a set of pads TpB and TpB # connected to the left side of the cable 32 will be described. Pad T
The set of pB and TpB # is the pad TpA and TpA #
Since the configuration is almost the same as that of the set, the different points will be mainly described.

At the middle point of the terminating resistor R1, a pad TpBi
As is not connected, for example, a resistor of 5 kΩ and a capacitor of 250 pF are connected in parallel with the ground potential. Since the resistance of 5 kΩ is higher than that of the terminating resistor R1, the middle point of the terminating resistor R1 is in a floating state close to a so-called floating state.

In the communication IC 12, the pads TpB and TpB
B # is connected to a cable (twisted pair line) 32, respectively. Further, similarly to the communication IC 22 described above, it has a current driver 42 and differential voltage detectors 43, 44, 45. However, a common-mode voltage detector 47 is provided instead of the common-mode voltage detector 46.

The common-mode voltage detector 47 has two pads TpB and TpB.
A comparison is made between the potential at the midpoint of the resistor R2 connected between pB # and a reference potential, for example, 0.8 V, and it is determined whether or not the cable 32 is connected according to the comparison result.

FIGS. 4A to 4C show the current driver 4 when transmitting packet data or arbitration.
FIG. 4 is a diagram for explaining the operation of FIG. 2 and is a simplified diagram of FIG. 3.

FIG. 4A is a diagram for explaining the operation of the current driver 42 when transmitting packet data "0" or arbitration "0".

The case where the current driver 42 of the node N1 transmits packet data "0" or arbitration "0" and the node N2 receives it will be described. The current driver 42 draws 4 mA from the outside to the + terminal,
Flow 4 mA out of the terminal.

The twisted pair wire has two terminating resistors R1
Are connected in parallel, the respective termination resistors R1
, A current flows by 2 mA. The direction of the current is from the-terminal to the + terminal, and a negative current flows.

The node N2 detects the differential voltage of the twisted pair line, that is, the voltage across the terminating resistor R1. The voltage at both ends of the terminating resistor R1 is −2 mA × (55Ω + 55Ω) = − 220 mV. Differential voltage detectors 43, 44, 45 at node N2
When FIG. 3 detects the differential voltage of −220 mV, it can be determined that the partner node N1 has transmitted packet data “0” or arbitration “0”.

FIG. 4B is a diagram for explaining the operation of the current driver 42 when transmitting packet data "1" or arbitration "1". The current driver 42 outputs 4 mA from the + terminal to the outside, and −
4 mA is drawn into the terminal.

The twisted pair wire has two terminating resistors R1
Are connected in parallel, the respective termination resistors R1
, A current flows by 2 mA. The direction of the current is from the + terminal to the − terminal, and a positive current flows.

The voltage across the terminating resistor R1 is +2 mA ×
(55Ω + 55Ω) = + 220 mV. When the differential voltage detector of the node N2 detects the differential voltage of +220 mV, it can be determined that the partner node N1 has transmitted the packet data “1” or the arbitration “1”.

FIG. 4C shows arbitration "Z".
FIG. 7 is a diagram for explaining an operation of the current driver 42 when transmitting the current signal.

If both the + terminal and the-terminal of the current driver 42 are opened inside the current driver 42, no current flows to either the + terminal or the-terminal to the outside. No current flows through the two terminating resistors R1.

The voltage at both ends of the terminating resistor R1 is 0 mA × (55Ω + 55Ω) = 0V. When the differential voltage detector of the node N2 detects the differential voltage of 0 V, it can be determined that the partner node N1 has transmitted the arbitration “Z”.

Next, as a communication phase, a speed signal in addition to packet data and arbitration will be described. The speed signal has three communication speeds of 10
It is used when setting any one of 0 Mbps, 200 Mbps, and 400 Mbps.

FIG. 5 is a waveform diagram showing a speed signal when the communication speed is set to 200 Mbps.

The speed signal is “ON” or “O”
FF "is a binary logic, and is transmitted and received in combination with each arbitration value.

FIG. 3 shows the speed signals "OFF", "ON", and "OF" when the arbitration is "0".
F ", the speed signal" OFF "," ON "," OFF "when the arbitration is" 1 ", and the speed signal" OF "when the arbitration is" Z ".
The waveform of the differential voltage of the twisted pair line and the waveform of the in-phase voltage of the twisted pair line in each case of “F”, “ON”, and “OFF” are shown.
All may be used when specifying 00 Mbps.

The differential voltage VD of the twisted pair line is a voltage detected by the differential voltage detectors 44 and 45 (FIG. 3), and as described with reference to FIGS. Depends on value. The differential voltage is −220 mV when the arbitration is “0”, is +220 mV when the arbitration is “1”, and is 0 V when the arbitration is “Z”.

The common-mode voltage VC of the twisted pair line is a voltage detected by the common-mode voltage detector 46 (FIG. 3). When the speed signal is "OFF", it is 1.85 V ± 0 V, and the speed signal is "ON". 1.85V-
192.5 mV. 1.85 V is a bias value, which is the potential of the pad TpBias (see FIG. 3).

FIGS. 6A to 6C are diagrams for explaining the operation of the current driver 42 when transmitting the combination of the arbitration and the speed signal, and are simplified diagrams of FIG.

By transmitting the following combination of arbitration and speed signal, the communication speed is reduced to 2
00 Mbps can be set.

FIG. 6A shows arbitration "0".
FIG. 9 is a diagram for explaining the operation of the current driver 42 when transmitting a combination of the speed signal "ON" and the speed signal "ON".

In order to turn on the speed signal, the current driver 4 corresponding to the pads TpB and TpB #
2 supplies the current (see FIG. 3). Pads TpA and Tp
The current driver 42 corresponding to A # cannot supply a current for turning the speed signal “ON”. The reason will be described later.

The current driver 42 is a current driver connected to the pads TpB and TpB # of the node N1, and is connected to the cable 32. Terminating resistors R1 are connected to both ends of the cable 32, respectively. The case where the current driver 42 of the node N1 transmits a combination of the arbitration “0” and the speed signal “ON”, and the node N2 receives it will be described.

The current driver 42 has a positive terminal of 7.5 mA.
Is drawn out, and a current of 0.5 mA is swept out from the minus terminal, so that when subtracted, a current of 7 mA is drawn in from the outside. The 7 mA current is supplied from the middle point of the terminating resistor R1 by the buffer 41 (FIG. 3) at the node N2.

In FIG. 3, a buffer 41 includes a pad T
An in-phase current is supplied to the middle point of the terminating resistor R1 connected to pA and TpA #. In order to turn the speed signal “ON”, the current driver 42 connected to the pads TpB and TpB # drives the current and causes the in-phase current to flow.

Among the terminating resistors R1 of the node N2, a current of 5.5 mA flows through the 55Ω resistor on the + terminal side, and a current of 1.5 mA flows through the 55Ω resistor on the − terminal side. A current of (0.5 + 1.5) mA = 2 mA flows from the negative terminal side to the positive terminal side through the terminating resistor R1 of the node N1.

The node N2 is connected to the differential voltage detectors 44, 45
By detecting the differential voltage of the twisted pair line (FIG. 3), the value of the arbitration can be determined. The differential voltage is a voltage applied to the terminating resistor R1. The voltages applied to the respective terminal resistors R1 at both ends of the cable 32 are the same.

The voltage applied to the terminating resistor R1 of the node N1 is -2 mA × (55Ω + 55Ω) = − 220 mV.

The voltage applied to the terminating resistor R1 at the node N2 is -5.5 mA × 55Ω + 1.5 mA × 55Ω = −220
mV.

The differential voltage detectors 44 and 45 at the node N2
When FIG. 3 detects the differential voltage of −220 mV, it can be determined that the partner node N1 has transmitted arbitration “0”.

The node N2 is connected to the common mode voltage detector 46.
By detecting the common mode voltage of the twisted pair wire (FIG. 3), the value of the speed signal can be determined.
The common-mode voltage is, as shown in the following equation, a reference bias Tp.
It can be represented by the magnitude of the voltage drop with respect to Bias (1.85 V). The voltage drop is a voltage drop of an in-phase voltage, and is a voltage drop caused by a current of 7 mA flowing through a parallel circuit of two 55Ω resistors. The current of 7 mA is 5.5
Although the current is divided into mA and 1.5 mA, the voltage drop is the same regardless of the current dividing ratio. The split ratio is -220 as described above.
It is related to the magnitude of the differential voltage of mV.

TpBias−7 mA × 55Ω ÷ 2 = TpBias−192.5 mV The common-mode voltage detector 46 (FIG. 3) of the node N 2 is TpBias.
When s-192.5 mV is detected, it can be determined that the partner node N1 has transmitted the speed signal “ON”.

FIG. 6B shows arbitration "1".
FIG. 9 is a diagram for explaining the operation of the current driver 42 when transmitting a combination of the speed signal "ON" and the speed signal "ON".
6A, the direction of the current is reversed, and the sign of the detected differential voltage is reversed.

The current driver 42 is 0.5 m from the + terminal.
The current of A is swept out, and a current of 7.5 mA is drawn into the-terminal.

A current of 7 mA is supplied from the buffer 41 (FIG. 3) of the node N2 to the middle point of the terminating resistor R1 of the node N2. Among the terminating resistors R1 of the node N2, a current of 1.5 mA flows through a 55Ω resistor on the + terminal side, and a current of 5.5 mA flows through a 55Ω resistor on the − terminal side. A current of 2 mA flows through the terminating resistor R1 of the node N1 from the + terminal side to the − terminal side.

The node N2 can determine the value of arbitration by detecting the differential voltage of the twisted pair line. The differential voltage is a voltage applied to the terminating resistor R1.

The voltage applied to the terminating resistor R1 at the node N1 is +2 mA × (55Ω + 55Ω) = + 220 mV.

Similarly, the voltage applied to the terminating resistor R1 of the node N2 is +5.5 mA × 55 Ω−1.5 mA × 55 Ω = + 220
mV.

When node N2 detects a differential voltage of +220 mV, it can be determined that partner node N1 has transmitted arbitration "1".

The node N2 can determine the value of the speed signal by detecting the common mode voltage of the twisted pair line. The common-mode voltage can be expressed by the following equation as in the case of FIG. The current of 7 mA is 1.5 m
A is divided into 5.5 mA and A, and the voltage drop is the same as in FIG. 6A regardless of the shunt ratio.

TpBias−7 mA × 55Ω ÷ 2 = TpBias−192.5 mV When the node N 2 detects a common mode voltage of TpBias−192.5 mV, it can be determined that the partner node N 1 has transmitted the speed signal “ON”. .

FIG. 6C shows arbitration "Z".
FIG. 9 is a diagram for explaining the operation of the current driver 42 when transmitting a combination of the speed signal "ON" and the speed signal "ON".
In this case, the differential voltage becomes 0 V, and the common mode voltage becomes TpBi.
as-192.5 mV.

In the current driver 42, a current of 3.5 mA is drawn from the outside to the + terminal, and a current of 3.5 mA is drawn from the outside to the-terminal.

A current of 7 mA is supplied to the middle point of the terminating resistor R1 of the node N2 from the buffer 41 (FIG. 3) of the node N2. Of the terminating resistor R1 of the node N2, a current of 3.5 mA flows through the 55Ω resistor on the + terminal side, and a current of 3.5 mA flows through the 55Ω resistor on the − terminal side. No current flows through the terminating resistor R1 of the node N1.

The node N2 can determine the value of arbitration by detecting the differential voltage of the twisted pair line. The differential voltage is a voltage applied to the terminating resistor R1.

The voltage applied to the terminating resistor R1 of the node N1 is also 0A × (55Ω + 55Ω) = 0V.

The voltage applied to the terminating resistor R1 of the node N2 is +3.5 mA × 55Ω-3.5 mA × 55Ω = 0 V.

When node N2 detects the differential voltage of 0 V, it can be determined that partner node N1 has transmitted arbitration "Z".

The node N2 can determine the value of the speed signal by detecting the common mode voltage of the twisted pair line. The common mode voltage is shown in FIG.
As in the case of (B), it can be expressed by the following equation.

TpBias−7 mA × 55Ω ÷ 2 = TpBias−192.5 mV When the node N 2 detects a common mode voltage of TpBias−192.5 mV, it can be determined that the partner node N 1 has transmitted the speed signal “ON”. .

[0070]

FIG. 7 is a diagram showing an internal configuration of a communication IC package.

The communication IC 53 has an IC chip 52 and a lead frame (IC pin) 54 connected thereto. The IC chip 52 has a core circuit unit 51 and a pad Tp connected thereto. The core circuit unit 51 includes internal cells such as a current driver 42 and a differential voltage detector 43, for example. The pad Tp is, for example, a pad TpA, TpA
#, TpBias, TpB, TpB #.

Wiring 5 connecting core circuit portion 51 and pad Tp
5 (for example, Al wiring) has a thin wiring and a complicated wiring path, so that its wiring resistance is relatively large at 10Ω to 50Ω. On the other hand, the wiring 56 (for example, Au wiring) connecting the pad Tp and the lead frame 54 and the lead frame 5
4 (for example, Cu wiring) has a relatively small wiring resistance of several mΩ. Since the resistance of the wiring 56 is small, there is no need to consider other influences, but the resistance of the wiring 55 is relatively large and adversely affects others. The adverse effects will be described below.

FIG. 8 is a circuit diagram of the communication IC 12 in consideration of the wiring resistance R3 between the core circuit section 51 and the pad Tp.

The communication IC 12 comprises a core circuit 51 and five pads TpA, TpA #, TpBias, TpB, Tp.
pB #. The core circuit 51 includes pads TpA and TpA.
The current buffer 42 connected to pA #, three differential voltage detectors 43, 44, 45, a common mode voltage detector 46, and a resistor R
2, a current buffer 42 connected to the pads TpB and TpB #, three differential voltage detectors 43, 44, 45, a comparator 47, and a resistor R2.

The wiring resistance R3 between the five pads Tp and the core circuit portion 51 is about 10Ω to 50Ω, respectively.
However, since almost no current flows between the pad TpBias and the common-mode voltage detector 46, there is no need to consider the wiring resistance between them. The wiring resistance R3 has an adverse effect on the differential voltage and the common mode voltage of the twisted pair line. Next, an adverse effect on the differential voltage will be described with reference to FIGS. 9 and 10, and an adverse effect on the common-mode voltage will be described with reference to FIGS.

FIG. 9 shows a case where there is no wiring resistance (R3 = 0).
FIG. 10 is a diagram for explaining a differential voltage of (Ω), and FIG. 10 is a diagram for explaining a differential voltage when there is a wiring resistance (R3 = 50Ω).

FIG. 9 is a circuit diagram when there is no wiring resistance, and is a simplified view of FIG. As in the case shown in FIG. 4B, the current driver 42 of the node N1 transmits 4 mA from the + terminal to transmit the arbitration “1”.
And outputs 4 mA to the-terminal. The current driver 42 of the node N2 is, as in the case shown in FIG.
To transmit arbitration “0”, connect 4 terminal to + terminal.
mA is input, and 4 mA is output from the-terminal. Since arbitration is full-duplex communication (two-way communication), the nodes N1 and N2 can transmit simultaneously.

The 4 mA current output from the + terminal of the current driver 42 at the node N1 is directly input to the + terminal of the current driver 42 at the node N2. The 4 mA current output from the negative terminal of the current driver 42 of the node N2 is directly input to the negative terminal of the current driver 42 of the node N1. The pad TpB and the pad TpA are short-circuited,
Since the pads TpB # and TpA # are short-circuited, no current flows through the terminating resistor R1.

The differential voltage detector 43 at the node N1 detects 0 V because no current flows through the terminating resistor R1.
If its own node N1 is not driving current, that is, transmitting arbitration "Z", and the differential voltage detector 43 detects 0V,
2 can be determined to be transmitting arbitration “Z” (see FIG. 4A).

Here, since its own node N1 is transmitting arbitration “1”, the differential voltage detector 4
When 3 detects 0V, it can be determined that the partner node N2 is transmitting arbitration "0".

FIG. 10 shows a structure in which 50 is provided between the core circuit portion and the pad.
FIG. 4 is a circuit diagram when there is a wiring resistance R3 of Ω, and is a simplified view of FIG. 3.

As in the case of FIG. 9, the current driver 42 of the node N1 outputs 4 mA from the + terminal and inputs 4 mA to the-terminal to transmit arbitration "1". The current driver 42 of the node N2 inputs 4 mA to the + terminal and outputs 4 mA from the − terminal to transmit arbitration “0”.

The pads TpB and TpA are short-circuited,
Since the pads TpB # and TpA # are short-circuited, no current flows through the terminating resistor R1. However, a current of +4 mA flows through the wiring resistance R3 (= 50Ω) between the + terminal of the current driver 42 and the pad TpB, and the wiring resistance R3 (= 50Ω) between the − terminal of the current driver 42 and the pad TpB #. ) Has a current of +4 mA.

The differential voltage detector 43 at the node N1 detects 0V when there is no wiring resistance R3 (FIG. 9), but detects the differential voltage represented by the following equation when there is the wiring resistance R3. The differential voltage detected by the differential voltage detector 43 corresponds to a potential difference between the + terminal and the − terminal of the current driver 42.

+4 mA × 50 Ω + 4 mA × 50 Ω = + 400 mV Although the differential voltage detector 43 should originally detect 0 V, it detects +400 mV due to the influence of the wiring resistance R 3. If the differential voltage detector 43 detects a differential voltage of +400 mV, it is erroneously recognized that the partner node N2 is transmitting arbitration "1".

Further, since the differential voltage fluctuates due to the influence of the wiring resistance R3, it is necessary to take measures to absorb the fluctuation. If the allowable voltage range is widened to absorb the fluctuation of the differential voltage, the setting margin of the voltage threshold must be reduced.

FIG. 11 shows the case where there is no wiring resistance (R3 = 0).
FIG. 12 is a diagram for explaining the common-mode voltage when the wiring resistance is present (R3 = 50Ω).

FIG. 11 is a circuit diagram when there is no wiring resistance, and is a simplified view of FIG. As in the case shown in FIG. 6B, the current driver 42 of the node N1 outputs 0.5 mA from the + terminal to transmit a combination of the arbitration “1” and the speed signal “ON”, and outputs the − terminal. Input 7.5mA.

The buffer 41 of the node N2 has a pad Tp
A current of 7 mA is supplied to the middle point of the terminating resistor R1 via Bias. Of the terminating resistor R1 at the node N2, a current of 1.5 mA flows through a 55Ω resistor on the + terminal side, and a current of 5.5 mA flows through a 55Ω resistor on the − terminal side. Node N1
A current of 2 mA flows from the positive terminal to the negative terminal through the terminating resistor R1.

At the midpoint CP of the resistor R2 at the node N1, a common mode voltage of the twisted pair line is generated. When transmitting a combination of the arbitration “1” and the speed signal “ON”, the common mode voltage is TpBias−192.5 mV
(See FIG. 6B).

The comparator 47 of the node N1 detects that the cable 32 has not been connected.
When the cable 32 is unplugged, TpBi is transmitted from the opposite node N2.
Since as is not applied, it is detected that the in-phase potential of the cable, that is, the potential of the comparator 47 drops to near 0V. Therefore, the threshold value is set to, for example, 0.8 V
Set to.

Although TpBias has been described as being constant at 1.85 V, TpBias can take a value of at least 1.165 V when viewed from node N1 in consideration of the ground drop between opposing nodes in the IEEE1394 standard. That is guaranteed. Here, for convenience of explanation,
A case where TpBias is 1.165 V will be described.

The potential of the middle point CP of the resistor R2 of the node N1 is TpBias−192.5mV = 1.165V−192.5mV = 0.9725V. Since this value is higher than the set threshold value 0.8V,
The node N1 can determine that the cable 32 is connected to itself. While the cable 32 is connected to the node N1, the comparator 47 outputs “L”.

FIG. 12 shows a structure in which 50 is provided between the core circuit portion and the pad.
FIG. 4 is a circuit diagram when there is a wiring resistance R3 of Ω, and is a simplified view of FIG. 3.

As in the case of FIG. 11, the current driver 42 of the node N1 outputs 0.5 mA from the + terminal and transmits 7 mA to the − terminal to transmit the combination of the arbitration “1” and the speed signal “ON”. Input 5 mA.

When there is no wiring resistance R3, the following potential is generated at the middle point CP of the resistance R2 of the node N1, as described above.

TpBias− (7 mA × 55Ω ÷ 2) = TpBias−192.5 mV On the other hand, when the wiring resistance R3 is 50Ω, the following potential is generated at the middle point CP of the resistance R2 of the node N1.

TpBias− {7mA × (55Ω + 50Ω)} 2) = TpBias−367.5mV = 1.165V−367.5mV = 0.7975V The comparator 47 of the node N1 has a negative terminal of the potential 0.7975V of the middle point CP. Is input, and the reference potential 0.
8V is input. Therefore, the comparator 47 outputs a logic “H”.

When the comparator 47 outputs "H",
The node N1 erroneously recognizes that the cable 32 is not connected to itself.

If the in-phase voltage of the twisted pair line fluctuates, the operating points of all the voltage detectors (comparators) fluctuate. Not only the common-mode voltage detector but also the voltage threshold of the differential voltage detector fluctuates.

An object of the present invention is to provide a current-driven communication circuit which is less adversely affected by wiring resistance between a core circuit portion and a pad.

[0102]

SUMMARY OF THE INVENTION A current-driven communication circuit according to the present invention includes a core including a current driver for driving a current for transmitting a signal and a voltage detector for detecting a voltage for receiving a signal. A circuit portion, a bonding pad for leading a signal line to the outside, and wiring for connecting the core circuit portion and the bonding pad, wherein the wiring is connected to the current driver for flowing a large current from the same bonding pad. A current path and a wiring including a non-current path to the voltage detector that transmits a small current or transmits a voltage without flowing a current, wherein the current path and the non-current path are separated from each other outside the core circuit unit. It has an independent and separate wiring portion.

The wiring for connecting the core circuit portion and the bonding pad is divided into a current path and a non-current path. The current path has a large voltage drop because a large current flows. The non-current path has little or no voltage drop because a small current flows or no current flows. If the current path wiring and the non-current path wiring are separately provided outside the core circuit section, the branch point of the current path and the non-current path can be placed near the bonding pad or on the bonding pad. Thus, the voltage detector connected to the non-current path can detect the voltage with almost no adverse effect due to the voltage drop in the current path.

[0104]

FIG. 13 is a circuit diagram of a communication IC 12 according to a first embodiment of the present invention.

The communication IC 12 comprises a core circuit 51 and five pads TpA, TpA #, TpBias, TpB, Tp.
pB #. The core circuit 51 includes pads TpA and TpA.
The current buffer 42 connected to pA #, three differential voltage detectors 43, 44, 45, a common mode voltage detector 46, and a resistor R
2, a current buffer 42 connected to the pads TpB and TpB #, three differential voltage detectors 43, 44, 45, a comparator 47, and a resistor R2.

The pads TpA and TpA # are connected to the current driver 42 via a path 61 and to the voltage detectors 43, 44, 45 and 46 via a path 62, respectively. The pads TpB and TpB # are also connected to the current driver 42 by a path 61, respectively, and the voltage detector 4 is connected by a path 62.
3, 44, 45 and 47.

The path 61 is a path connected from the pad Tp to the current driver 42, and is a path through which a current flows. The path 62 is a path connected from the branch point PP on the path 61 to the voltage detectors 43, 44, 45, 46, 47, and is a path through which no current flows.

The wiring resistance R3 of the current path 61 is about 10Ω
５０50Ω. Since no current flows through the non-current path 62, the wiring resistance of the non-current path 62 has almost no adverse effect.

In the conventional communication IC 12 (FIG. 8), a path to the current driver 42 and a path to the voltage detector 43 and the like are branched inside the core circuit section 51. Communication I of this embodiment
In C12 (FIG. 13), the paths 61 and 62 branch at a branch point PP near the pad Tp. Preferably, the core circuit unit 5
It is preferable to provide a branch point PP at a position closer to the pad Tp than a middle point of the path 61 on the path 61 connecting the 1 and the pad Tp. More preferably, the branch point PP is the pad Tp
That is on top.

FIG. 14 is a diagram showing the difference between the thickness of the current path 61 and the thickness of the non-current path 62.

The current path 61 includes pads TpA, TpA #
And a path for connecting the current driver 42. The wiring resistance R3 is made as small as possible by making the path thicker. If the path is made thicker, the wiring resistance R3 can be reduced to about 10Ω.

The non-current path 62 includes pads TpA, TpA
# Is a path for connecting the # to the voltage detector 43, etc., so that no current needs to be thickened because current does not flow. The advantage is greater when trying.

The cross-sectional area of the current path 61 is
Is preferably at least twice the cross-sectional area of The electric resistance of the current path 61 is preferably equal to or less than half the electric resistance of the non-current path 62.

FIG. 15 shows a communication IC 12 according to this embodiment.
FIG. 16 is a diagram for explaining the common-mode voltage detection of the communication IC 12 according to the present embodiment.

FIG. 15 is a diagram showing that the adverse effect of the differential voltage (see FIG. 10) on the conventional communication IC 12 has been eliminated by this embodiment.

The current driver 42 of the node N1 and the pad T
There is a wiring resistance R3 between pB and TpB #. In the conventional communication IC (FIG. 10), the differential voltage detector 43 is connected between the current driver 42 and the wiring resistance R3. In the communication IC according to the present embodiment (FIG. 15), the differential voltage detector 43
Is connected between the wiring resistance R3 and the pads TpB, TpB #.

As in the case of FIG. 10, the current driver 42 of the node N1 outputs 4 mA from the + terminal and inputs 4 mA to the-terminal in order to transmit arbitration "1". The current driver 42 of the node N2 inputs 4 mA to the + terminal and outputs 4 mA from the − terminal to transmit arbitration “0”.

No current flows through the terminating resistor R1. However, the wiring resistance R3 (= 50) connected to the pad TpB
Ω), and a current of +4 mA also flows through the wiring resistance R3 (= 50Ω) connected to the pad TpB #. Here, the direction of the current flowing out of the + terminal of the current driver 42 is +, and the direction of the current flowing in the + terminal is-. Further, the direction flowing into the negative terminal of the current driver 42 is defined as +, and the direction flowing out of the negative terminal is defined as-.

The differential voltage detector 43 at the node N1 detects the branch point P between the pads TpB, TpB # and the wiring resistance R3.
Since it is connected to P, it does not detect a voltage drop in the wiring resistance R3. Further, similarly to the case of FIG. 10, since no current flows through the terminating resistor R1, there is no voltage drop at the terminating resistor R1. Differential voltage detector 43 of node N1
Can detect a normal differential voltage of about 0V.

Since its own node N1 is transmitting arbitration “1”, the differential voltage detector 43
Is detected, it can be determined that the other node N2 is transmitting arbitration "0".

FIG. 16 is a diagram showing that the adverse effect of the common-mode voltage (see FIG. 12) on the conventional communication IC has been eliminated by this embodiment.

The current driver 42 of the node N1 and the pad T
There is a wiring resistance R3 between pB and TpB #. The conventional communication IC (FIG. 12) has a current driver 42 and a wiring resistance R
3, a resistor R2 is connected. The communication IC (FIG. 16) according to the present embodiment includes a wiring resistor R3 and a pad TpB,
The resistor R2 is connected between TpB #.

As in the case of FIG. 12, the current driver 42 of the node N1 outputs 0.5 mA from the + terminal and transmits 7 mA to the − terminal to transmit the combination of the arbitration “1” and the speed signal “ON”. Input 5 mA.

Since the resistance R2 is connected to the branch point PP between the pads TpB, TpB # and the wiring resistance R3, the potential of the middle point CP of the resistance R2 is not affected by the voltage drop in the wiring resistance R3. .

The potential of the middle point CP of the resistor R2 of the node N1 is TpBias− (7 mA × 55Ω ÷ 2) = TpBias−192.5 mV = 1.165 V−192.5 mV = 0.9725V.

In the comparator 47 at the node N1,
The potential of the middle point CP of 0.9725 V is input to the − terminal,
A reference potential of 0.8 V is input to the terminal. Comparator 4
The output of 7 is logic "L".

Since the comparator 47 outputs a logic "L", the node N1 can determine that the cable 32 is connected to the node N1 normally.

FIG. 17 is a circuit diagram of the communication IC 12 according to the second embodiment of the present invention. First Embodiment (FIG. 13)
Then, the resistor R2 is provided in the core circuit unit 51. In the second embodiment (FIG. 17), the resistor R2 is provided outside the core circuit unit 51 and near the pad Tp.

In the second embodiment, the core circuit 51
Includes a current driver 42 and three differential voltage detectors 43, which do not include the resistor R2 and are connected to the pads TpA and TpA #.
44, 45, common-mode voltage detector 46, pads TpB and TpB.
It has a current driver 42 connected to pB #, three differential voltage detectors 43, 44, 45, and a comparator 47.

The path 61 is a path connected from the pad Tp to the current driver 42, and is a path through which a current flows. The path 62 is connected from the pad Tp to the voltage detectors 43 and 4.
4, 45, 46, and 47, which are paths through which no current flows.

FIG. 18 is a diagram showing the difference between the thickness of the current path 61 and the thickness of the non-current path 62. The current path 61 is
This is a path for connecting the pads TpA, TpA # and the current driver 42, and the wiring resistance R3 is made as small as possible by making the path thicker. The non-current path 62 is a path for connecting the pads TpA, TpA # to the voltage detector 43 and the like, and narrows the path to reduce the area occupied by the path.

The cross-sectional area of the current path 61 is
5 times or more the cross-sectional area of The electric resistance of the current path 61 is preferably 1/10 or less of the electric resistance of the non-current path 62.

Since the electric circuit diagram of the second embodiment is the same as that of the first embodiment, similarly to the first embodiment, the differential circuit and the common-mode voltage given by the wiring resistance R3 are reduced. Can be avoided (see FIGS. 15 and 16).

In the first embodiment (FIG. 13), the resistor R2 is provided in the core circuit portion 51, and in the second embodiment (FIG. 17), the resistor R2 is provided outside the core circuit portion 51 and at a remote position. It is provided in. The resistor R2 is formed as a well resistor on the substrate to reduce the occupied area.

According to the second embodiment, if the resistor R2 is provided at a position distant from the core circuit section 51, the substrate noise caused by the operation of the core circuit section 51 is less likely to affect the resistor R2. However, since the resistance R2 is high, the middle point of the resistance R2 becomes high impedance. Since the path for connecting the high impedance node and the comparator 46 or 47 is long, there is a disadvantage that the path is susceptible to noise. The path is preferably shielded.

According to the first embodiment, if the resistor R2 is provided in the core circuit section 51, the path of the high impedance node connected to the middle point of the resistor R2 is shortened, and the resistance to noise is relatively high. However, the resistance R2 is easily affected by substrate noise due to the operation of the core circuit unit 51.

According to the first or second embodiment, when the pad and the core circuit are connected, the pad and the core circuit are branched into a current path and a non-current path on or near the pad. It is possible to avoid an adverse effect due to the wiring resistance between them. Even if the wiring resistance exists, it can be correctly detected as the differential voltage and the common mode voltage when there is no wiring resistance. By correctly detecting the differential voltage and the common mode voltage, packet data, arbitration, cable connection detection, and the like can be normally recognized.

In addition, it is possible to prevent the fluctuation of the differential voltage and the common mode voltage due to the wiring resistance R3 and to suppress the fluctuation of the threshold value of the voltage detector (comparator).

Although the case where the connection between the core circuit portion and the pad is branched into a current path and a non-current path has been described, the non-current path is not limited to a path through which no current flows at all. If the current flowing in the non-current path is smaller than the current flowing in the current path, the effect of the present embodiment can be obtained. Preferably, the current flowing through the non-current path is 1 / the current flowing through the current path.
10 or less.

Further, the present invention is not limited to the case where the current path and the non-current path are connected to the same pad. The current path and the non-current path may be connected to different pads, and the two pads may be connected to the same lead frame (the inner leads) by bonding wires. Alternatively, the current path and the non-current path may be connected to different pads, and the two pads may be connected to different lead frames (inner leads). In that case, the two lead frames (the inner leads thereof) may be connected to the same outer lead or the corresponding external pins may be connected.

Further, in the first and second embodiments, the IE
The communication is not limited to the communication of the EE1394 standard. It can be applied to other serial communication and parallel communication.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0143]

As described above, according to the present invention,
When connecting the core circuit portion and the bonding pad, the current path and the non-current path are connected separately, and the wiring portions of the two paths are separately provided outside the core circuit portion. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a communication network based on the IEEE 1394 standard.

FIG. 2 is a circuit diagram showing a detailed configuration of an upper half of FIG. 1;

FIG. 3 is a circuit diagram showing a detailed configuration of a lower half of FIG. 1;

4 (A) transmits packet data “0” or arbitration “0”, FIG. 4 (B) transmits packet data “1” or arbitration “1”, and FIG. 4 (C) transmits arbitration “Z” FIG. 9 is a diagram for explaining the operation of the current driver when performing the operation.

FIG. 5 is a waveform diagram showing a speed signal when the communication speed is set to 200 Mbps.

6A is a combination of arbitration “0” and a speed signal “ON”, FIG. 6B is a combination of arbitration “1” and a speed signal “ON”, and FIG. 6C is an arbitration “ FIG. 9 is a diagram for explaining an operation of the current driver when transmitting a combination of “Z” and a speed signal “ON”.

FIG. 7 is a diagram showing an internal configuration of a communication IC package.

FIG. 8 is a circuit diagram of a conventional communication IC.

FIG. 9 is a circuit diagram of a communication IC for detecting a differential voltage when there is no wiring resistance.

FIG. 10 is a circuit diagram of a communication IC for detecting a differential voltage when there is a wiring resistance between a core circuit unit and a pad.

FIG. 11 is a circuit diagram of a communication IC for detecting a common-mode voltage when there is no wiring resistance.

FIG. 12 is a circuit diagram of a communication IC for detecting a common-mode voltage when a wiring resistance exists between a core circuit unit and a pad.

FIG. 13 is a circuit diagram of the communication IC according to the first embodiment of the present invention.

FIG. 14 is a diagram illustrating the difference between the thickness of a current path and the thickness of a non-current path in the present embodiment.

FIG. 15 shows a communication I for detecting a differential voltage according to the present embodiment.
It is a circuit diagram of C.

FIG. 16 shows a communication I for detecting a common mode voltage according to the present embodiment.
It is a circuit diagram of C.

FIG. 17 is a circuit diagram of a communication IC according to a second embodiment of the present invention.

FIG. 18 is a diagram illustrating a difference between the thickness of a current path and the thickness of a non-current path in the present embodiment.

[Explanation of symbols]

 N1, N2 Communication nodes 12, 22 Communication IC 13, 23 External circuit 31, 32 Communication cable 41 Buffer 42 Current driver 43, 44, 45 Differential voltage detector 46, 47 In-phase voltage detector Tp bonding pad 51 Core circuit Part 52 IC chip 53 communication IC 54 lead frame 61 current path 62 non-current path

Claims (6)

[Claims] 1. A current driver for driving a current for transmitting a signal, a core circuit including a voltage detector for detecting a voltage for receiving a signal, and a bonding pad for leading a signal line to the outside. A wiring for connecting the core circuit portion and the bonding pad, wherein a current path for flowing a large current from the same bonding pad to the current driver and a small current or a voltage without flowing a current. And a wiring including a non-current path for transmitting the voltage to the voltage detector, wherein the current path and the non-current path outside the core circuit unit have separate wiring portions independent of each other. 2. The current path and the non-current path include a common portion connected to the bonding pad.
The current-driven communication circuit according to claim 1. 3. The current-driven communication circuit according to claim 1, wherein the electric resistance of the current path is equal to or less than half the electric resistance of the non-current path. 4. A current driver for driving a current for transmitting a signal, a core circuit including a voltage detector for detecting a voltage for receiving a signal, and a first and a second circuit for guiding a signal line to the outside. A second bonding pad; a first wiring connecting the current driver in the core circuit unit and the first bonding pad; a second wiring connecting a voltage detector in the core circuit unit and the second bonding pad And a current-driven communication circuit having: 5. The current according to claim 4, further comprising: a lead frame including a plurality of leads; and a bonding wire for connecting the first and second bonding pads to the same lead in the lead frame. Driven communication circuit. 6. A lead frame including first and second leads; a bonding wire for connecting each of the first and second bonding pads to the first and second leads; 5. The current-driven communication circuit according to claim 4, further comprising: a lead connection wiring for connecting the first and second leads.