JPH0537332A - Buffer circuit - Google Patents

Abstract

PURPOSE:To prevent a breakdown of a buffer by providing a circuit for detecting an error state that logic of an input side and an output side of the buffer is inconsistent, and controlling its buffer to a distble state. CONSTITUTION:An output of an error detecting circuit 4 is inputted to an enable terminal 11 of a buffer 1, and when the output of the circuit 4 becomes an H level, the buffer 1 becomes a disable (invalid) state. The moment a power source is turned on, even if each part of the circuit is executing any operation, as the case may be, the output of the circuit 4 becomes an H level, the buffer 1 becomes a disable state, and in order to prevent it, a pull-up resistance 7 is provided. As a result, the circuit 4 outputs an L level. Accordingly, the buffer 1 becomes an enable state, and when an input of the buffer 1 is an H level, outputs of the buffers 1, 2 and 3 all output an H level, and thereafter, the level is varied in accordance with the input of the buffer 1.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a buffer circuit, and more particularly to a buffer circuit used in a communication device, a computer, or the like.

[0002]

2. Description of the Related Art Generally, a buffer is used in a communication device, a digital computer or the like which applies a digital logic circuit. A buffer is also used when designing a digital device that requires a package mounting state using a logic circuit configured as an integrated circuit, in addition to a logic circuit configured using individual electric components.

Conventionally, in a CMOS buffer circuit for output and reception, which is used between gate arrays having different power supplies, when the power supply of the gate array on the receiving side is turned off, the buffer becomes a low impedance state and a large current flows. Will end up. There is a drawback in that the current causes a failure such as the buffer on the output side being broken. In addition, in order to prevent this, there is a drawback that it is necessary to externally attach a TTL buffer to the gate array on the receiving side.

[0004]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and an object thereof is to provide a buffer circuit capable of preventing the destruction of an output buffer without providing an external circuit. That is.

[0005]

According to the buffer circuit of the present invention, the power supply is cut off from a first buffer, a second buffer which receives an output of the first buffer and operates by a power supply different from the first buffer. When a signal that causes the output line of the first buffer to have a low level and the output line to have a high level is input to the first buffer, the first buffer is disabled. And a control circuit.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram of an embodiment of a buffer circuit according to the present invention. In the figure, the buffer circuit of the present embodiment is a tri-state type CMOS buffer 1 provided in the gate array 5, and a tri-state type CMOS buffer 1 provided in the gate array 6 with the output of the buffer 1 as an input.
It is configured to include a CMOS buffer 3. The gate arrays 5 and 6 are different from each other in the source of power supply, and thus the buffer 1 and the buffer 3 operate by the supply of different power.

In the normal operation, the signal is transmitted as it is from the buffer 1 to the buffer 3. However, there is a case where only the power supply of the gate array 6 is cut off. In such a case, the input side of the buffer 3 becomes low impedance, and the buffer 1 may be damaged.

Therefore, in the present embodiment, the error detection circuit 4
Is provided. The error detection circuit 4 is a circuit in which the output is high only when the input of the buffer 1 is high and the output of the buffer 2, that is, the output of the buffer 1 is low. For example, as shown in FIG. 2, the AND circuit 40 and an inverter 41 provided at one input of the AND circuit 40 are provided, the output of the buffer 2 is input to the inverter 41, and the input of the buffer 1 is directly input to the AND circuit. Enter in 40.

Returning to FIG. 1, the output of the error detection circuit 4 is
When the error detection circuit 4 is input to the enable terminal 11 of the buffer 1 and the output of the error detection circuit 4 becomes high level, the buffer 1 is disabled (disabled). The enable terminals of the tristate buffers 2 and 3 are always at low level.

The operation of the circuit of this embodiment having such a configuration will be described with reference to FIG. FIG. 3 is a time chart showing the operation of each unit in FIG. First, when the power supplies of the gate arrays 5 and 6 change from the off state to the on state (time A), the output of the buffer 2 becomes high level by the pull-up resistor 7.

That is, it is not known how each part of the circuit operates at the moment when the power is turned on, and in some cases, the output of the error detection circuit becomes high level and the buffer 1 is disabled. .. The pull-up resistor 7 is provided to prevent this. The resistance value may be set to 250 [Ω] or more when the drive capacity of the buffer 1 is about 20 [mA].

As a result, the error detection circuit 4 outputs a low level. Therefore, the buffer 1 is enabled, and when the input of the buffer 1 is set to the high level, the outputs of the buffers 1, 2, and 3 all output the high level. After that, the level changes according to the input of the buffer 1.

Here, when only the power source of the gate array 6 is turned off (time B), the input of the buffer 3 is in the low impedance state, and the output of the buffer 2 is in the low level. The error detection circuit 4 detects this and outputs a high level. As a result, a high level is input to the enable terminal 11 of the buffer 1, the output of the buffer 1 is closed, and no current flows.

After that, when the power source of the gate array 6 is restored (time C), the output of the buffer 2 becomes high level,
Buffer 1 is enabled again.

Even when the buffer to be protected from destruction is an inverter buffer, the destruction can be similarly prevented by changing the internal configuration of the error detection circuit. In other words, when the output line of the buffer to be protected is at low level (low level) and a signal that makes the output line at high level (high level) is input to that buffer, the buffer is controlled to the disable state. It is only necessary to provide an error detection circuit that does this.

[0017]

As described above, according to the present invention, the buffer is destroyed by providing a circuit for detecting an error state in which the logics of the input side and the output side of the buffer are inconsistent and controlling the buffer in the disabled state. The effect is that it can be prevented.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a buffer connection circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration example of an error detection circuit in FIG.

FIG. 3 is a time chart showing the operation of each part in the figure.

[Explanation of symbols]

 1,2,3 buffer 4 error detection circuit 5,6 gate array

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 19/0175

Claims (1)

Claim: What is claimed is: 1. A first buffer, a second buffer that receives an output of the first buffer as an input, and operates by a power supply different from that of the first buffer, and the power supply is in a disconnected state. When the output line of the first buffer is at a low level and a signal that makes the output line at a high level is input to the first buffer, the control for disabling the first buffer And a buffer circuit.