JPH01253315A - Bidirectional buffer - Google Patents

Abstract

PURPOSE:To prevent the output short circuit state of a bidirectional buffer even to the control of the input signal where plural bidirectional buffers are set under the output states at one time by securing a function where the short circuit state of the output is detected and prevented by one bidirectional buffer itself. CONSTITUTION:An EX-NOR 5 inhibits the detection of an output short circuit state for a period covering the change of an output signal 11 applied to a bidirectional buffer 1 through the delay time of a delay circuit 4. A NAND 6 delivers a low level after detecting an output short circuit state in an output state of the buffer 1. However the output short circuit state is not detected when the signal 11 applied to the buffer 1 changes and when an enable signal 12 of the the circuit 1 changes to a high level from a low level. An enable signal control circuit 2 sets forcibly the buffer 1 under an input state when the output of an output short circuit state detecting circuit 8 is kept at a low level. Thus it is possible to prevent the short circuit caused between an input/ output shared terminal of the buffer 1 and a VDD or GND line even to the input control signals with which plural bidirectional buffer circuits are set under the output states at one time.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to bidirectional buffers.

[Conventional technology]

Generally, bidirectional buffers are used in circuits configured by connecting the input/output common terminals of multiple bidirectional buffers in common, and in such circuits, multiple bidirectional buffers are in the output state and are not output. If the values are different, an excessive current may flow from the bidirectional buffer outputting a high level to the bidirectional buffer outputting a low level, resulting in destruction or performance deterioration of the bidirectional buffer.

A circuit diagram of a conventional bidirectional buffer is shown in FIG.

In the figure, when the bidirectional buffer 14 inputs a high level to the enable signal 17, the bidirectional buffer 14 becomes a trap output state, and the output signal 16 to the bidirectional buffer is outputted to the input/output common terminal 181C.

Also, when a low level is input to the enable signal 17,
The bidirectional buffer 14 is in an input state, and the signal input to the input/output common terminal 18 becomes the input signal 15 from the bidirectional buffer. The input signal 15 from the bidirectional buffer has the same value as the output signal 16 to the bidirectional buffer when bidirectional 14 is in the output state.

For this reason, in conventional circuits configured by connecting multiple input/output terminals of this type of bidirectional buffer, only one bidirectional buffer is always in the output state and the other bidirectional buffers are in the input state. Such input signal control was performed.

[Problem to be solved by the invention]

The conventional bidirectional buffer described above has the disadvantage that if input signal control is performed such that multiple commonly connected bidirectional buffers are in the output state, the bidirectional buffer may be destroyed or its performance degraded. The drawback is that the input signal control circuit of the direct buffer must be designed strictly.

In addition, since the output short circuit of the bidirectional buffer is avoided by input signal control, even if the input/output common terminal of the bidirectional buffer occurs a short circuit with the power supply (VDD) line or the ground (GND) line, it will be detected and It also has the disadvantage that it cannot be prevented.

It is an object of the present invention to solve the above-mentioned drawbacks and to provide a method for input control signals that cause multiple bidirectional buffers to be output at the same time.
In addition, even if the input/output common terminal of a bidirectional buffer causes a short circuit with the VDD line or GND line, one bidirectional buffer itself has a function to detect the output short circuit state and prevent it. It is possible to provide a bidirectional buffer that is compatible with the buffer.

[Means to solve the problem]

The bidirectional buffer of the present invention is a bidirectional buffer that performs bidirectional control using an enable signal, and inputs an input signal from the bidirectional buffer, an output signal to the bidirectional buffer, and an enable signal of the bidirectional buffer. , an output short-circuit state detection circuit that detects an output short-circuit state of the bidirectional buffer when the bidirectional buffer is in an output state; and an output short-circuit state detection circuit that receives an enable signal of the bidirectional buffer and an output signal of the output short-circuit state detection circuit. and an enable signal control circuit that forcibly brings the bidirectional buffer into an input state when the bidirectional buffer is in an output short-circuit state.

〔Example〕

Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a bidirectional buffer according to an embodiment of the present invention. In this figure, EX-OR3゜EX-NOR5
, NAND6. The delay circuits 4 and 7 constitute an output short-circuit state detection circuit 8.

The delay time of the delay circuit 4 is set to the time from when the output signal 11 to the bidirectional buffer 1 changes until the input signal 10 from the bidirectional buffer 1 becomes stable when the bidirectional buffer 1 is in the output state. put.

Further, the delay time of the delay circuit 7 is set to the time from when the bidirectional buffer 1 switches from the input state to the output state until the input signal 10 from the bidirectional buffer becomes stable.

EX-OR3 receives the input signal 10 from the bidirectional buffer and the output signal 11 to the bidirectional buffer, and monitors whether the values match.

The delay circuit 4 receives the output signal 11 to the bidirectional buffer as an input.

EX-NOR 5 receives the output signal 11 to the bidirectional buffer and the output signal of the delay circuit 4 as input, and is in an output short-circuit state during the delay time of the delay circuit 4 after the output signal 11 to the bidirectional buffer changes. Prohibit detection.

The delay circuit 7 receives the bidirectional buffer enable signal 12 as an input.

NAND6 receives the output signals of EX-OR3, EX-NOR5, and delay circuit 7 as inputs, and outputs a low level when detecting an output short-circuit state in the output state of bidirectional buffer I. However, when the output signal 11 to the bidirectional buffer changes and when the enable tl12 of the bidirectional buffer changes from low level to high level, the output short state is not detected.

AND2 is an enable signal control circuit which receives as input the enable signal of the bidirectional buffer and the output signal of the output short-circuit state detection circuit.

The enable signal control circuit forces the bidirectional buffer 1 into the input state when the output of the output short-circuit state detection circuit is at a low level.

〔Effect of the invention〕

As is clear from the above description, by replacing the bidirectional buffer of the present invention with a conventional bidirectional buffer, multiple bidirectional buffers can be This also has the effect of preventing short-circuited outputs of bidirectional buffers for input signal control in which the buffers are in the output state at the same time. Further, even if the input/output common terminal of the bidirectional buffer is short-circuited with the VDD line or the GND line, this can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a bidirectional buffer according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a conventional bidirectional buffer. 1...Bidirectional buffer, 2...AND
, 3...EX-OR, 4...delay circuit, 5...EX-NOR. 6...NAND, 7...Delay circuit, 8
... Output short circuit state detection circuit, 9 ... Enable signal control circuit, 10 ... Input signal from bidirectional buffer, 11 ... To bidirectional buffer output signal, 12... bidirectional buffer enable signal, 13... bidirectional buffer input/output common terminal, 14... bidirectional buffer, 15...
...Input signal from bidirectional buffer, 16...
- Output signal to bidirectional buffer, 17... Bidirectional buffer enable signal, 18... Bidirectional buffer input/output common terminal. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] In a bidirectional buffer that performs bidirectional control using an enable signal, an input signal from the bidirectional buffer, an output signal to the bidirectional buffer, and an enable signal of the bidirectional buffer are input, and the bidirectional buffer is in an output state. an output short-circuit state detection circuit that detects an output short-circuit state of the bidirectional buffer when A bidirectional buffer comprising: an enable signal control circuit that forces the bidirectional buffer into an input state at certain times.