JP2009164933A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology of detecting an abnormal state (output short circuit state and input-open state) of an external terminal without increasing costs in a semiconductor integrated circuit. <P>SOLUTION: The semiconductor integrated circuit (MCU) includes a plurality of I/O circuits (IO1 to IO4), a monitor target designating circuit (DPSEL), and an abnormality detecting circuit (PCDET). The plurality of I/O circuits (IO1 to IO4) are provided corresponding to a plurality of external terminals (P1 to P4). The monitor target designating circuit (DPSEL) variably designates a monitor target external terminal from among the plurality of external terminals (P1 to P4). The abnormality detecting circuit (PCDET) detects the output short circuit state of the monitor target external terminal when the I/O circuit corresponding to the monitor target external terminal functions as an output circuit, and detects the input-open state of the monitor target external terminal when the I/O circuit corresponding to the monitor target external terminal functions as an input circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit such as a microcontroller (MCU).

  In a system using an LSI (Large Scale Integration) such as a microcontroller, an output short circuit (signal collision) may occur at an external terminal of the LSI due to a software or hardware design error. In an LSI, when an output short circuit occurs at an external terminal, an overcurrent flows through the internal element (transistor) connected to the external terminal, causing damage to the internal element or shortening the lifetime of the internal element. Arise. For this reason, a technique for detecting an output short-circuit state of an external terminal in an LSI has been proposed (see, for example, Patent Documents 1 and 2).

  FIG. 11 shows a conventional example (part 1) of an input / output port circuit of an LSI. The input / output port circuit of FIG. 11 corresponds to that disclosed in Patent Document 2 (FIG. 5), and includes a direction register DDR, a data register PDR, and an input / output circuit IO. The direction register DDR is set to “0” when the input / output circuit IO is used as an input circuit, and is set to “1” when the input / output circuit IO is used as an output circuit. The signal DDRO is a signal indicating the set value of the direction register DDR. When the input / output circuit IO is used as an output circuit, the data register PDR is set to “0” when the signal set to “0” is output from the external terminal P, and the signal set to “1” is output. When outputting from the external terminal P, it is set to “1”. The signal PDRO is a signal indicating the set value of the data register PDR.

  The input / output circuit IO includes a NAND circuit NAa, inverters IVa and IVb, a NOR circuit NRa, a PMOS transistor PMa, and an NMOS transistor NMa. The NAND circuit NAa sets the signal NAaO to “1” regardless of the signal PDRO when the signal DDRO is set to “0”, and outputs the signal PDRO when the signal DDRO is set to “1”. Inverted and output as signal NAaO. Inverter IVa inverts signal DDRO and outputs the inverted signal as signal IVaO. The NOR circuit NRa inverts the signal PDRO when the signal IVaO is set to “0” and outputs the inverted signal PDRO, and outputs the signal NRaO regardless of the signal PDRO when the signal IVaO is set to “1”. NRaO is set to “0”. The PMOS transistor PMa is connected between a signal line INOUT (signal line for transmitting the signal INOUT) connected to the external terminal P and a power supply line VDD (for example, 3V). The NMOS transistor NMa is connected between the signal line INOUT and the ground line GND (0 V). The signal NAaO is input to the control terminal of the PMOS transistor PMa, and the signal NRaO is input to the control terminal of the NMOS transistor NMa. Inverter IVb inverts signal INOUT and outputs the inverted signal as signal IVbO.

  In the input / output circuit IO having such a configuration, when the signal DDRO is set to “1”, the signals NAaO and NRaO are set to a logical value opposite to that of the signal PDRO. When the signal PDRO is set to “0”, the signals NAaO and NRaO are set to “1”, so that the PMOS transistor PMa is turned off and the NMOS transistor NMa is turned on. As a result The signal INOUT output from the external terminal P is set to “0”. When the signal PDRO is set to “1”, the signals NAaO and NRaO are set to “0”, so that the PMOS transistor PMa is turned on and the NMOS transistor NMa is turned off. As a result, the signal INOUT output from the external terminal P is set to “1”. Thus, the input / output circuit IO functions as an output circuit when the signal DDRO is set to “1”. On the other hand, when the signal DDRO is set to “0”, the signal NAaO is set to “1” and the signal NRaO is set to “0” regardless of the signal PDRO. The transistor NMa is turned off. As a result, the signal INOUT input to the external terminal P is output to the internal circuit of the LSI via the inverter IVb. Thus, the input / output circuit IO functions as an input circuit when the signal DDRO is set to “0”.

  According to the input / output port circuit as described above, one external terminal can be used as both an input terminal and an output terminal in a program, and flexible programming becomes possible. In addition, since one external terminal can be used as both an input terminal and an output terminal, the number of external terminals can be reduced, and as a result, an effect of realizing cost reduction can be obtained.

  FIG. 12 shows a conventional example (part 2) of the input / output port circuit of the LSI. The input / output port circuit of FIG. 12 is an output short circuit detection circuit (output short circuit state of the external terminal P) implemented by the comparators CMPa, CMPb, inverter IVc, AND circuits ANa, ANb, and OR circuit ORa in the input / output port circuit of FIG. This circuit is configured by adding a circuit for detecting the above. This output short circuit detection circuit corresponds to that disclosed in Patent Document 1 (FIG. 2).

  The comparator CMPa sets the signal CMPaO to “0” when the voltage of the signal INOUT is higher than the threshold voltage VTHa, and sets the signal CMPaO to “1” when the voltage of the signal INOUT is lower than the threshold voltage VTHa. The comparator CMPb sets the signal CMPbO to “0” when the voltage of the signal INOUT is lower than the threshold voltage VTLa (VTLa <VTHa), and sets the signal CMPbO to “1” when the voltage of the signal INOUT is higher than the threshold voltage VTLa. Set. Inverter IVc inverts signal NAaO and outputs it as signal NAaOX. The AND circuit ANa sets the signal SSH to “0” regardless of the signal CMPaO when the signal NAaOX is set to “0”, and outputs the signal CMPaO when the signal NAaOX is set to “1”. Output as signal SSH. The AND circuit ANb sets the signal SSL to “0” regardless of the signal CMPbO when the signal NRaO is set to “0”, and outputs the signal CMPbO when the signal NRaO is set to “1”. Output as signal SSL. The OR circuit ORa sets the signal SS to “0” when both the signals SSH and SSL are set to “0”, and sets at least one of the signals SSH and SSL to “1”. The signal SS is set to “1”.

  In the output short circuit detection circuit having such a configuration, when the input / output circuit IO functions as an output circuit (when the signal DDRO is set to “1”), the output short circuit state of the external terminal P is as follows: Is detected. When the signal PDRO is set to “1” (when the PMOS transistor PMa of the input / output circuit IO is in an on state), a signal set to “0” is output from another LSI to the external terminal P. If there is such a system design error, an output short circuit occurs at the external terminal P. In such a case, although the external terminal P (signal line INOUT) is driven to “1” (high level) by the input / output circuit IO, the external terminal P (signal line INOUT) is set to “1” by another LSI. Since it is driven to 0 ″ (low level), a large current flows through the PMOS transistor PMa of the input / output circuit IO, and a large current also flows through the transistors of another LSI. At this time, the voltage of the signal INOUT is lower than when no output short-circuit occurs at the external terminal P. Therefore, for example, the threshold voltage VTHa is set 0.5 V lower than the voltage of the power supply line VDD, and the voltage of the signal INOUT decreases from the voltage of the power supply line VDD as the output short circuit occurs at the external terminal P. When it becomes lower, the signal CMPaO is set to “1” in the comparator CMPa. When the signal PDRO is set to “1”, since the signal NAaOX is set to “1”, the signal SSH is set to “1” as the signal CMPaO is set to “1”. As a result, the signal SS is set to “1”. Thereby, the output short circuit state of the external terminal P is detected.

  Further, when the signal PDRO is set to “0” (when the NMOS transistor NMa of the input / output circuit IO is in the on state), a signal set to “1” from another LSI with respect to the external terminal P If there is a system design error that is output, an output short circuit occurs at the external terminal P. In such a case, the external terminal P (signal line INOUT) is driven to “1” by another LSI even though the external terminal P (signal line INOUT) is driven to “0” by the input / output circuit IO. Therefore, a large current flows through the NMOS transistor NMa of the input / output circuit IO, and a large current also flows through the transistor of another LSI. At this time, the voltage of the signal INOUT is higher than that when no output short circuit occurs at the external terminal P. Therefore, for example, the threshold voltage VTLa is set 0.5 V higher than the voltage of the ground line GND, and the voltage of the signal INOUT rises from the voltage of the ground line GND as the output short circuit occurs at the external terminal P, and the threshold voltage VTLa When it becomes higher, the signal CMPbO is set to “1” in the comparator CMPb. When the signal PDRO is set to “0”, the signal NRaO is set to “1”, so that the signal SSL is set to “1” as the signal CMPbO is set to “1”. As a result, the signal SS is set to “1”. Thereby, the output short circuit state of the external terminal P is detected.

  However, in reality, even when an output short circuit does not occur at the external terminal P, when the signal INOUT transitions with a change in the setting value of the data register PDR, the voltage of the signal INOUT is lower than the threshold voltage VTHa. There exists a state or a state where the voltage of the signal INOUT is higher than the threshold voltage VTLa. Therefore, it is necessary to provide a timing control circuit or the like for avoiding that the signal SS is set to “1” due to the transition of the signal INOUT accompanying the change of the setting value of the data register PDR.

  FIG. 13 shows a conventional example (part 3) of the input / output port circuit of the LSI. The input / output port circuit of FIG. 13 is similar to the input / output port circuit of FIG. 11 in that AND circuits ANc to ANf, inverters IVd to IVh, delay circuits DLYa and DLYb, ENOR circuits ENRa and ENRb, comparators CMPc and CMPd, NMOS transistors NMb and NMc. In addition, an output short circuit detection circuit embodied by PMOS transistors PMb and PMc is added. This output short circuit detection circuit corresponds to that disclosed in Patent Document 2 (FIG. 4).

  The AND circuit ANc sets the signal ANcO to “0” regardless of the signal PDRO when the signal DDRO is set to “0”, and outputs the signal PDRO when the signal DDRO is set to “1”. Output as signal ANcO. Inverter IVd inverts signal PDRO and outputs it as signal PDROX. The AND circuit ANd sets the signal ANdO to “0” regardless of the signal PDROX when the signal DDRO is set to “0”, and outputs the signal PDROX when the signal DDRO is set to “1”. Output as signal ANdO. The delay circuit DLYa delays the signal ANcO for a predetermined time and outputs it as the signal DLYaO. The delay circuit DLYb delays the signal ANdO for a predetermined time and outputs it as the signal DLYbO. The ENOR circuit ENRa sets the signal ENRaO to “0” when the logical values of the signals PDRO and DLYaO do not match, and sets the signal ENRaO to “1” when the logical values of the signals PDRO and DLYaO match. The ENOR circuit ENRb sets the signal ENRbO to “0” when the logical values of the signals PDROX and DLYbO do not match, and sets the signal ENRbO to “1” when the logical values of the signals PDROX and DLYbO match. The AND circuit ANe sets the signal ANeO to “0” regardless of the signal PDRO when the signal ENRaO is set to “0”, and outputs the signal PDRO when the signal ENRaO is set to “1”. Output as signal ANeO. The AND circuit ANf sets the signal ANfO to “0” regardless of the signal PDROX when the signal ENRbO is set to “0”, and outputs the signal PDROX when the signal ENRbO is set to “1”. Output as signal ANfO. Inverter IVe inverts signal ANeO and outputs it as signal ANeOX. Inverter IVf inverts signal ANfO and outputs it as signal ANfOX.

  The comparator CMPc sets the signal CMPcO to “0” when the voltage of the signal INOUT is higher than the threshold voltage VTHb, and sets the signal CMPcO to “1” when the voltage of the signal INOUT is lower than the threshold voltage VTHb. The comparator CMPd sets the signal CMPdO to “0” when the voltage of the signal INOUT is lower than the threshold voltage VTLb (VTLb <VTHb), and sets the signal CMPdO to “1” when the voltage of the signal INOUT is higher than the threshold voltage VTLb. Set. The NMOS transistor NMb and the PMOS transistor PMb are connected in parallel between the signal line CMPcO and the signal line DET. The signal ANeO is input to the control terminal of the NMOS transistor NMb, and the signal ANeOX is input to the control terminal of the PMOS transistor PMb. The NMOS transistor NMc and the PMOS transistor PMc are connected in parallel between the signal line CMPdO and the signal line DET. The signal ANfO is input to the control terminal of the NMOS transistor NMc, and the signal ANfOX is input to the control terminal of the PMOS transistor PMc. The inverter IVg inverts the signal DET and outputs it as the signal DETX, and the inverter IVh inverts the signal DETX and outputs it as the signal DET. That is, the inverters IVg and IVh implement a latch circuit that holds the signal DET.

  In the output short circuit detection circuit having such a configuration, when the input / output circuit IO functions as an output circuit (when the signal DDRO is set to “1”), the output short circuit state of the external terminal P is as follows: Is detected. When the signal PDRO is set to “0”, the signal ANeO is set to “0” and the signal ANeOX is set to “1”, so that the NMOS transistor NMb and the PMOS transistor PMb are turned off. Therefore, the signal CMPcO is not involved in the signal DET. When the signal PDRO is set to “0”, the signal PDROX is set to “1”, so that the signals ANdO and DLYbO are set to “1” and the signal ENRbO is set to “1”. The As a result, the signal ANfO is set to “1” and the signal ANfOX is set to “0”, so that the NMOS transistor NMc and the PMOS transistor PMc are turned on. Therefore, the signal CMPdO is output as the signal DET. When an output short circuit occurs in the external terminal P in such a state, the signal CMPdO changes from “0” to “1” when the voltage of the signal INOUT rises from the voltage of the ground line GND and becomes higher than the threshold voltage VTLb. As a result, the signal DET transitions from “0” to “1”. Thereby, the output short circuit state of the external terminal P is detected.

  When the signal PDRO transitions from “0” to “1”, the signal PDROX transitions from “1” to “0”. Therefore, the signal ANfO transitions from “1” to “0”, and the signal ANfOX transitions from “0”. Transition to “1”. As a result, the NMOS transistor NMc and the PMOS transistor PMc are turned off, and as a result, the signal CMPdO does not participate in the signal DET. When the signal PDRO transitions from “0” to “1”, the signal ANcO transitions from “0” to “1”. After the delay time of the delay circuit DLYa elapses after the signal ANcO transitions, the signal DLYaO Transition from “0” to “1”. Accordingly, since the signal ENRaO changes from “0” to “1”, the signal ANeO changes from “0” to “1”, and the signal ANeOX changes from “1” to “0”. Therefore, the NMOS transistor NMb and the PMOS transistor PMb are turned on, and as a result, the signal CMPcO is output as the signal DET. That is, in the period from when the signal PDRO transitions until the delay time of the delay circuit DLYa elapses, the NMOS transistor NMb and the PMOS transistor PMb remain in the off state, and the signal CMPcO is not involved in the signal DET. When the signal PDRO transitions from “0” to “1”, the signal INOUT transitions from “0” to “1”. When the signal INOUT transits from “0” to “1”, there is a state in which the voltage of the signal INOUT is lower than the threshold voltage VTHb even when the output short circuit does not occur at the external terminal P. However, when the delay time of the delay circuit DLYa is set longer than the transition time of the signal INOUT (signal transition time of the external terminal P), the signal transition state of the external terminal P is detected as the output short-circuit state of the external terminal P. It is avoided.

  On the other hand, when the signal PDRO is set to “1”, since the signal PDROX is set to “0”, the signal ANfO is set to “0”, and the signal ANfOX is set to “1”. As a result, the NMOS transistor NMc and the PMOS transistor PMc are turned off. Therefore, the signal CMPdO is not involved in the signal DET. Further, when the signal PDRO is set to “1”, the signals ANcO and DLYaO are set to “1”, and the signal ENRaO is set to “1”. As a result, the signal ANeO is set to “1” and the signal ANeOX is set to “0”, so that the NMOS transistor NMb and the PMOS transistor PMb are turned on. Therefore, the signal CMPcO is output as the signal DET. When an output short circuit occurs at the external terminal P in such a state, the signal CMPcO changes from “0” to “1” when the voltage of the signal INOUT drops from the voltage of the power supply line VDD and becomes lower than the threshold voltage VTHb. As a result, the signal DET transitions from “0” to “1”. Thereby, the output short circuit state of the external terminal P is detected.

  When the signal PDRO transitions from “1” to “0”, the signal ANeO transitions from “1” to “0”, and the signal ANeOX transitions from “0” to “1”. As a result, the NMOS transistor NMb and the PMOS transistor PMb are turned off, and as a result, the signal CMPcO does not participate in the signal DET. Further, when the signal PDRO transitions from “1” to “0”, the signal PDROX transitions from “0” to “1”, so that the signal ANdO transitions from “0” to “1”, and the signal ANdO transitions. After the delay time of the delay circuit DLYb has elapsed, the signal DLYbO transitions from “0” to “1”. Accordingly, since the signal ENRbO changes from “0” to “1”, the signal ANfO changes from “0” to “1”, and the signal ANfOX changes from “1” to “0”. Therefore, the NMOS transistor NMc and the PMOS transistor PMc are turned on, and as a result, the signal CMPdO is output as the signal DET. That is, in the period from when the signal PDRO transitions until the delay time of the delay circuit DLYb elapses, the NMOS transistor NMc and the PMOS transistor PMc remain in the off state, and the signal CMPdO is not involved in the signal DET. When the signal PDRO transitions from “1” to “0”, the signal INOUT transitions from “1” to “0”. When the signal INOUT transitions from “1” to “0”, there is a state in which the voltage of the signal INOUT is higher than the threshold voltage VTLb even when the output short circuit does not occur at the external terminal P. However, setting the delay time of the delay circuit DLYb to be longer than the transition time of the signal INOUT prevents the signal transition state of the external terminal P from being detected as the output short-circuit state of the external terminal P.

  In addition to a technique for detecting an output short-circuit state of an external terminal in an LSI, a technique for detecting an abnormality in an input circuit due to an abnormality in a switch, a connector, or the like in an in-vehicle LSI or the like has also been proposed (for example, a patent (Ref. 3, 4).

  FIG. 14 shows a conventional example (No. 1) of an LSI input port circuit. The input port circuit of FIG. 14 is provided corresponding to an external terminal TERM connected to the ground line GND via a resistor Ra and a switch SWa, and includes resistors Rb, Rc, a switch SWb, a buffer BFa, and a level determination circuit CIRC. Configured. This input port circuit corresponds to that disclosed in Patent Document 3 (FIG. 2).

  The resistor Rb is connected between the signal line IN connected to the external terminal TERM and the power supply line VDD. The resistor Rc and the switch SWb are connected in series between the signal line IN and the power supply line VDD. The buffer BFa receives the signal IN and outputs a signal VB. The level determination circuit CIRC periodically controls the switch SWb via the signal Sa, and on / off state of the switch SWa and circuit abnormality (damage of the buffer BFa, etc.) based on the level (logic value) of the signal VB at that time ) Is determined. The level determination circuit CIRC outputs the signal Sb to the internal circuit of the LSI only when it is determined that the switch SWa is on and there is no circuit abnormality.

  In the input port circuit having such a configuration, when the resistance values of the resistors Ra, Rb, and Rc are in a relationship of Rc <Ra <Rb, and the switch SWa is in the on state and the switch SWb is in the off state, VB is set to “0”, and in other cases, the signal VB is set to “1”. Accordingly, the level determination circuit CIRC recognizes the level of the signal VB by turning off the switch SWb, and then recognizes the level of the signal VB by turning on the switch SWb, corresponding to the on / off state of the switch SWb. When the signal VB transitions, it is determined that the switch SWa is in the on state and there is no circuit abnormality, and the signal Sb is output.

  FIG. 15 shows a conventional example (part 2) of the input port circuit of the LSI. The input port circuit of FIG. 15 corresponds to that disclosed in Patent Document 4 (FIG. 2), and includes PMOS transistors PMd and PMe, NMOS transistors NMd and NMe, pull-up resistors Rd and Rf, pull-down resistors Re and Rg, and buffers. BFb, BFc, D-type flip-flops DFFa, DFFb, and a selector SELa are provided.

  The PMOS transistor PMd and the pull-up resistor Rd are connected in series between the signal line PINa connected to the external terminal and the power supply line VDD. The NMOS transistor NMd and the pull-down resistor Re are connected in series between the signal line PINa and the ground line GND. A signal TST is input to the control terminals of the PMOS transistor PMd and the NMOS transistor NMd. The PMOS transistor PMe and the pull-up resistor Rf are connected in series between the signal line PINb connected to an external terminal different from the signal line PINa and the power supply line VDD. The NMOS transistor NMe and the pull-down resistor Rg are connected in series between the signal line PINb and the ground line GND. A signal TST is input to the control terminals of the PMOS transistor PMe and the NMOS transistor NMe. The buffer BFb embodies an input circuit, receives the signal PINa, and outputs the signal BFbO to the internal circuit of the LSI. The buffer BFc implements an input circuit, receives the signal PINb, and outputs the signal BFcO to the internal circuit of the LSI. The D-type flip-flops DFFa and DFFb and the selector SELa implement a scan circuit that sequentially outputs the signals BFbO and BFcO to the outside of the LSI. The D-type flip-flop DFFa takes in the signal BFbO supplied to the input terminal D as the signal CLK input to the clock terminal CK transitions from “0” to “1”, and outputs the signal DFbO as the output terminal QFFaO. Output from. The selector SELa selects one of the signals DFFAO and BFcO according to the signal TSEL and outputs it as the signal SELaO. The D-type flip-flop DFFb takes in the signal SELaO input to the input terminal D as the signal CLK supplied to the clock terminal CK transitions from “0” to “1”, and outputs the signal SEFF as the output terminal QFFbO. Output from.

In the input port circuit having such a configuration, when a signal fixed to “0” is input to the external terminal connected to the signal line PINa (PINb) and the signal TST is set to “0”, the PMOS transistor PMd (PMe) ) Is turned on, and the pull-up resistor Rd (Rf) is connected to the signal line PINa (PINb). As a result, if the external terminal connected to the signal line PINa (PINb) is not in the input open state, the signal BFbO (BFcO) is set to “0”, and the external terminal connected to the signal line PINa (PINb) is input open. In the state, the signal BFbO (BFcO) is set to “1”. Further, when a signal fixed to “1” is input to the external terminal connected to the signal line PINa (PINb) and the signal TST is set to “1”, the NMOS transistor NMd (NMe) is turned on and a pull-down is performed. The resistor Re (Rg) is connected to the signal line PINa (PINb). As a result, if the external terminal connected to the signal line PINa (PINb) is not in the input open state, the signal BFbO (BFcO) is set to “1”, and the external terminal connected to the signal line PINa (PINb) is input open. In the state, the signal BFbO (BFcO) is set to “0”. Accordingly, the logical value of the signal TST is set according to the logical value of the signal input to the external terminals connected to the signal lines PINa and PINb, and the scan realized by the D-type flip-flops DFFA and DFFb and the selector SELa. By sequentially outputting the signals BFbO and BFcO to the outside of the LSI using a circuit, it is possible to confirm whether the external terminals connected to the signal lines PINa and PINb are open.
JP-A-60-200347 JP 2004-48341 A JP 60-41321 A Japanese Patent No. 3645748

  As described above with reference to FIGS. 12 to 15, a technique for detecting an output short circuit state or an input open state of an external terminal in an LSI has been proposed. However, there are the following problems.

  In the circuit configuration of FIG. 12, since it is necessary to provide an output short circuit detection circuit for each external terminal, there is a problem that the chip area of the LSI is increased and the cost is significantly increased. Furthermore, there is a problem that no countermeasure is taken with respect to the signal transition state of the external terminal, and the signal transition state of the external terminal may be detected as an output short-circuit state of the external terminal. In the circuit configuration of FIG. 13, countermeasures are taken for the signal transition state of the external terminals. However, as in the circuit configuration of FIG. 12, an output short circuit detection circuit must be provided for each external terminal. There is a problem that the cost increases significantly due to an increase in the cost. In the circuit configuration of FIG. 14 and the circuit configuration of FIG. 15 as well, it is necessary to provide an input open detection circuit (input abnormality detection circuit) for each external terminal, which increases the chip area of the LSI and significantly increases the cost. There's a problem.

  The present invention has been made in view of such problems, and provides a technique for detecting an abnormal state (an output short circuit state and an input open state) of an external terminal without increasing the cost in a semiconductor integrated circuit. With the goal.

  The semiconductor integrated circuit includes a plurality of input / output circuits, a monitoring target specifying circuit, and an abnormality detection circuit. The plurality of input / output circuits are provided corresponding to the plurality of external terminals. The monitoring target designating circuit variably designates the monitoring target external terminal from among the plurality of external terminals. The abnormality detection circuit detects an output short-circuit state of the monitored external terminal when the input / output circuit corresponding to the monitored external terminal functions as an output circuit, and the input / output circuit corresponding to the monitored external terminal is the input circuit. When the function is functioning as an input, the input open state of the monitored external terminal is detected. In such a semiconductor integrated circuit, since the abnormality detection circuit is shared by a plurality of external terminals, the chip area of the semiconductor integrated circuit can be reduced, and the function of detecting the abnormal state of the external terminals without increasing the cost Can be realized.

  In a semiconductor integrated circuit, it is possible to detect an abnormal state (an output short circuit state and an input open state) of an external terminal without increasing costs.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a first embodiment of the present invention. The microcontroller MCU according to the first embodiment includes direction registers DDR1 to DDR4, data registers PDR1 to PDR4, input / output circuits IO1 to IO4, a terminal selection circuit DPSEL, an abnormality detection circuit PCDET, and an abnormality detection control circuit PCDCTL. Yes. Although not shown, the microcontroller MCU is also equipped with a CPU (Central Processing Unit), a flash memory (program storage memory), a UART (Universal Asynchronous Receiver Transmitter), a timer, and the like.

  The direction register DDRi (i = 1, 2, 3, 4) is set to “0” when the input / output circuit IOi is used as an input circuit, and “1” when the input / output circuit IOi is used as an output circuit. Set to The signal DDRiO is a signal indicating the set value of the direction register DDRi. When the input / output circuit IOi is used as an output circuit, the data register PDRi is set to “0” when the signal set to “0” is output from the external terminal Pi, and the signal set to “1” is output. It is set to “1” when outputting from the external terminal Pi. The signal PDRiO is a signal indicating the set value of the data register PDRi.

  The input / output circuit IOi is provided corresponding to the external terminal Pi, and includes a NAND circuit NA1i, inverters IV1i and IV2i, a NOR circuit NR1i, a PMOS transistor PM1i, and an NMOS transistor NM1i. The NAND gate NA1i, inverters IV1i, IV2i, NOR circuit NR1i, PMOS transistor PM1i, and NMOS transistor NM1i in the input / output circuit IOi are connected in the following manner: NAND circuit NAa, inverters IVa, IVb, NOR circuit NRa in the input / output circuit IO The connection relationship between the PMOS transistor PMa and the NMOS transistor NMa is the same.

  The terminal selection circuit DPSEL variably designates the monitoring target external terminal from among the external terminals P1 to P4, outputs a signal corresponding to the monitoring target external terminal among the signals DDR1O to DDR4O as the signal DDRSO, and outputs the signals PDR1O to PDR4O. The signal corresponding to the monitoring target external terminal is output as the signal PDRSO, and the signal corresponding to the monitoring target external terminal is output as the signal INOUTSO among the signals INOUT1 to INOUT4. Details of the terminal selection circuit DPSEL will be described later with reference to FIG.

  The abnormality detection circuit PCDET detects the abnormal state (output short-circuit state and input open state) of the monitoring target external terminal based on the signals DDRSO, PDRSO, and INOUTSO only when the signal PCDEO is set to “1”. The abnormality detection circuit PCDET sets the signal DETSOO to “1” when detecting the output short-circuit state of the monitoring target external terminal, and sets the signal DETSIO to “1” when detecting the input open state of the monitoring target external terminal. To do. Details of the abnormality detection circuit PCDET will be described later with reference to FIGS.

  The abnormality detection control circuit PCDCTL outputs a signal PCDEO indicating permission / prohibition of the detection operation of the abnormality detection circuit PCDET. The signal PCDEO is set to “0” when the detection operation of the abnormality detection circuit PCDET is prohibited, and is set to “1” when the detection operation of the abnormality detection circuit PCDET is permitted. The abnormality detection control circuit PCDCTL outputs an interrupt signal IRQPCD for the CPU based on the signals DETSOO and DETSIO. The details of the abnormality detection control circuit PCDCTL will be described later with reference to FIG.

  FIG. 2 shows the terminal selection circuit of FIG. The terminal selection circuit DPSEL includes a terminal selection control register DPSELCR, a decoder DEC1, and selectors SEL1 to SEL3. The terminal selection control register DPSELCR is a register for variably specifying the monitoring target external terminal from among the external terminals P1 to P4. The signal VDPSELCR is a signal indicating the set value of the terminal selection control register DPSELCR. The decoder DEC1 decodes the signal VDPSELCR and outputs signals PSEL1 to PSEL4. Specifically, the decoder DEC1 sets the signal PSEL1 (PSEL2, PSEL3, PSEL4) to “1” when the signal VDPSELCR is set to a logical value indicating the external terminal P1 (P2, P3, P4). The signals other than PSEL1 (PSEL2, PSEL3, PSEL4) in the signals PSEL1 to PSEL4 are set to “0”.

  The selector SEL1 includes switches SS11 to SS14. The switch SS11 (SS12, SS13, SS14) is connected between the signal line DDR1O (DDR2O, DDR3O, DDR4O) and the signal line DDRSO. The switch SS11 (SS12, SS13, SS14) is turned off when the signal PSEL1 (PSEL2, PSEL3, PSEL4) is set to “0”, and the signal PSEL1 (PSEL2, PSEL3, PSEL4) is set to “1”. Turns on when set. The selector SEL2 includes switches SS21 to SS24. The switch SS21 (SS22, SS23, SS24) is connected between the signal line PDR1O (PDR2O, PDR3O, PDR4O) and the signal line PDRSO. The switch SS21 (SS22, SS23, SS24) is turned off when the signal PSEL1 (PSEL2, PSEL3, PSEL4) is set to “0”, and the signal PSEL1 (PSEL2, PSEL3, PSEL4) is set to “1”. Turns on when set. The selector SEL3 includes switches SS31 to SS34. The switch SS31 (SS32, SS33, SS34) is connected between the signal line INOUT1 (INOUT2, INOUT3, INOUT4) and the signal line INOUTSO. The switch SS31 (SS32, SS33, SS34) is turned off when the signal PSEL1 (PSEL2, PSEL3, PSEL4) is set to “0”, and the signal PSEL1 (PSEL2, PSEL3, PSEL4) is set to “1”. Turns on when set.

  In the terminal selection circuit DPSEL having such a configuration, when the terminal selection control register DPSELCR is set to a register value indicating the external terminal P1 (P2, P3, P4), the signal PSEL1 (PSEL2, PSEL3, PSEL4) is output from the decoder DEC1. Set to “1”. As a result, the switch SS11 (SS12, SS13, SS14) is turned on in the selector SEL1, and the signal DDR1O (DDR2O, DDR3O, DDR4O) is output as the signal DDRSO, and the switch S21 (SS22, SS23, SS24) is output in the selector SEL2. The signal PDR1O (PDR2O, PDR3O, PDR4O) is output as the signal PDRSO in the on state, the switch SS31 (SS32, SS33, SS34) is turned on in the selector SEL3, and the signal INOUT1 (INOUT2, INOUT3, INOUT4) is the signal Output as INOUTSO.

  FIG. 3 shows the abnormality detection circuit of FIG. The abnormality detection circuit PCDET includes AND circuits AN1 to AN7, inverters IV3 to IV8, delay time control registers PCDDLYCR, variable delay circuits VDLY1 and VDLY2, threshold voltage generation circuits PCDVTG, comparators CMP1 and CMP2, NMOS transistors NM2, NM3, and PMOS transistor PM2. , PM3, NOR circuit NR2, switches SW1, SW2, pull-up resistor R1, and pull-down resistor R2.

  The AND circuit AN1 sets the signal AN1O to “0” regardless of the signal DDRSO when the signal PCDEO is set to “0”, and outputs the signal DDRSO when the signal PCDEO is set to “1”. Output as signal AN1O. The AND circuit AN2 sets the signal AN2O to “0” regardless of the signal PDRSO when the signal AN1O is set to “0”, and outputs the signal PDRSO when the signal AN1O is set to “1”. Output as signal AN2O. Inverter IV3 inverts signal PDRSO and outputs it as signal PDRSOX. The AND circuit AN3 sets the signal AN3O to “0” regardless of the signal PDRSOX when the signal AN1O is set to “0”, and outputs the signal PDRSOX when the signal AN1O is set to “1”. Output as signal AN3O. The delay time control register PCDDLYCR is a register for variably specifying the delay times of the variable delay circuits VDLY1 and VDLY2. For example, the delay time control register PCDDLYCR is set to a register value indicating one of the delay times TD1 to TD4 (TD1 <TD2 <TD3 <TD4). The signal VPCDDLYCR is a signal indicating the set value of the delay time control register PCDDLYCR. The variable delay circuit VDLY1 delays the signal AN2O by a time corresponding to the logical value of the signal VPCDDLYCR and outputs it as the signal VDLY1O. The variable delay circuit VDLY2 delays the signal AN3O by a time corresponding to the logical value of the signal VPCDDLYCR and outputs it as the signal VDLY2O. The AND circuit AN4 sets the signal AN4O to “0” when at least one of the signals AN2O and VDLY1O is set to “0”, and sets both the signals AN2O and VDLY1O to “1”. The signal AN4O is set to “1”. The AND circuit AN5 sets the signal AN5O to “0” when at least one of the signals AN3O and VDLY2O is set to “0”, and sets both the signals AN3O and VDLY2O to “1”. The signal AN5O is set to “1”. Inverter IV4 inverts signal AN4O and outputs it as signal AN4OX. Inverter IV5 inverts signal AN5O and outputs it as signal AN5OX.

  The threshold voltage generation circuit PCDVTG generates variable voltage threshold voltages VTH and VTL (VTL <VTH) only when the signal PCDEO is set to “1”. The comparator CMP1 sets the signal CMP1O to “0” when the voltage of the signal INOUTSO is higher than the threshold voltage VTH, and sets the signal CMP1O to “1” when the voltage of the signal INOUTSO is lower than the threshold voltage VTH. The comparator CMP2 sets the signal CMP2O to “0” when the voltage of the signal INOUTSO is lower than the threshold voltage VTL, and sets the signal CMP2O to “1” when the voltage of the signal INOUTSO is higher than the threshold voltage VTL. The NMOS transistor NM2 and the PMOS transistor PM2 are connected in parallel between the signal line CMP1O and the signal line DETSOO. The signal AN4O is input to the control terminal of the NMOS transistor NM2, and the signal AN4OX is input to the control terminal of the PMOS transistor PM2. The NMOS transistor NM3 and the PMOS transistor PM3 are connected in parallel between the signal line CMP2O and the signal line DETSOO. The signal AN5O is input to the control terminal of the NMOS transistor NM3, and the signal AN5OX is input to the control terminal of the PMOS transistor PM3. Inverter IV6 inverts signal DETSOO and outputs it as signal DETSOOX, and inverter IV7 inverts signal DETSOOX and outputs it as signal DETSOO. That is, the inverters IV6 and IV7 embody a latch circuit that holds the signal DETSOO.

  Inverter IV8 inverts signal PCDEO and outputs the inverted signal as PCDEOX. The NOR circuit NR2 inverts the signal DDRSO and outputs it as the signal NR2O when the signal PCDEOX is set to “0”, and the signal NRSO regardless of the signal DDRSO when the signal PCDEOX is set to “1”. NR2O is set to “0”. The switch SW1 and the pull-up resistor R1 are connected in series between the signal line INOUTSO and a power supply line VDD (for example, 3V). The switch SW2 and the pull-down resistor R2 are connected in series between the signal line INOUTSO and the ground line GND (0 V). The switches SW1 and SW2 are turned off when the signal NR2O is set to “0”, and are turned on when the signal NR2O is set to “1”. The AND circuit AN6 sets the signal AN6O to “0” when at least one of the signals CMP1O and CMP2O is set to “0”, and sets both the signals CMP1O and CMP2O to “1”. The signal AN6O is set to “1”. The AND circuit AN7 sets the signal DETSIO to “0” regardless of the signal AN6O when the signal NR2O is set to “0”, and outputs the signal AN6O when the signal NR2O is set to “1”. Output as signal DETSIO.

  In the abnormality detection circuit PCDET configured as described above, the detection operation of the abnormality detection circuit PCDET is permitted, and the input / output circuit corresponding to the monitored external terminal functions as an output circuit (the signal PCDEO is “1”). When the signal DDRSO is set to “1”), the output short-circuit state of the monitored external terminal is detected as follows. When the signal PDRSO is set to “0”, since the signal AN2O is set to “0”, the signal AN4O is set to “0”, and the signal AN4OX is set to “1”. The NMOS transistor NM2 and the PMOS transistor PM2 are turned off. Therefore, the signal CMP1O is not involved in the signal DETSOO. When the signal PDRSO is set to “0”, the signal PDRSOX is set to “1”, so that the signals AN3O and VDLY2O are set to “1”. As a result, the signal AN5O is set to “1” and the signal AN5OX is set to “0”, so that the NMOS transistor NM3 and the PMOS transistor PM3 are turned on. Therefore, the signal CMP2O is output as the signal DETSOO. Since the signal NR2O is set to “0”, the switches SW1 and SW2 are turned off. As a result, the pull-up resistor R1 and the pull-down resistor R2 are disconnected from the signal line INOUTSO. When an output short circuit occurs in the monitored external terminal in such a state, the signal CMP2O changes from “0” to “1” when the voltage of the signal INOUTSO rises from the voltage of the ground line GND and becomes higher than the threshold voltage VTL. As a result, the signal DETSOO changes from “0” to “1”. Thereby, the output short circuit state of the monitoring object external terminal is detected.

  When the signal PDRSO transits from “0” to “1”, the signal PDRSOX transits from “1” to “0”, so that the signal AN3O transits from “1” to “0”. As a result, the signal AN5O transits to “0”. The signal transitions from “1” to “0”, and the signal AN5OX transitions from “0” to “1”. As a result, the NMOS transistor NM3 and the PMOS transistor PM3 are turned off, and as a result, the signal CMP2O does not participate in the signal DETSOO. Further, when the signal PDRSO transits from “0” to “1”, the signal AN2O transits from “0” to “1”, and after the delay time of the variable delay circuit VDLY1 elapses after the signal AN2O transits, the signal VDLY1O Transition from “0” to “1”. As a result, the signal AN4O changes from “0” to “1” and the signal AN4OX changes from “1” to “0”, so that the NMOS transistor NM2 and the PMOS transistor PM2 are turned on. As a result, the signal CMP1O Is output as the signal DETSOO. That is, in the period from when the signal PDRSO transitions until the delay time of the variable delay circuit VDLY1 elapses, the NMOS transistor NM2 and the PMOS transistor PM2 remain in the off state, and the signal CMP1O is not involved in the signal DETSOO. When the signal PDRSO transits from “0” to “1”, the signal INOUTSO transits from “0” to “1”. When the signal INOUTSO transits from “0” to “1”, there is a state in which the voltage of the signal INOUTSO is lower than the threshold voltage VTH even when an output short circuit does not occur at the monitored external terminal. However, since the delay time of the variable delay circuit VDLY1 is set to be longer than the transition time of the signal INOUTSO (signal transition time of the monitoring target external terminal), the signal transition state of the monitoring target external terminal is the output short-circuit state of the monitoring target external terminal. Detecting as is avoided.

  On the other hand, when the signal PDRSO is set to “1”, since the signal PDRSOX is set to “0”, the signal AN3O is set to “0”. As a result, the signal AN5O is set to “0” and the signal AN5OX is set to “1”, so that the NMOS transistor NM3 and the PMOS transistor PM3 are turned off. Therefore, the signal CMP2O is not involved in the signal DETSOO. When the signal PDRSO is set to “1”, the signals AN2O and VDLY1O are set to “1”, so that the signal AN4O is set to “1” and the signal AN4OX is set to “0”. As a result, the NMOS transistor NM2 and the PMOS transistor PM2 are turned on. Therefore, the signal CMP1O is output as the signal DETSOO. If an output short circuit occurs in the monitored external terminal in such a state, the signal CMP1O changes from “0” to “1” when the voltage of the signal INOUTSO decreases from the voltage of the power supply line VDD and becomes lower than the threshold voltage VTH. As a result, the signal DETSOO changes from “0” to “1”. Thereby, the output short circuit state of the monitoring object external terminal is detected.

  When the signal PDRSO transits from “1” to “0”, the signal AN2O transits from “1” to “0”, so the signal AN4O transits from “1” to “0”, and the signal AN4OX transits from “0”. Transition to “1”. As a result, the NMOS transistor NM2 and the PMOS transistor PM2 are turned off, and as a result, the signal CMP1O does not participate in the signal DETSOO. Further, when the signal PDRSO transits from “1” to “0”, the signal PDRSOX transits from “0” to “1”, so that the signal AN3O transits from “0” to “1”, and the signal AN3O transits. Then, after the delay time of the variable delay circuit VDLY2 elapses, the signal VDLY2O changes from “0” to “1”. As a result, the signal AN5O changes from “0” to “1” and the signal AN5OX changes from “1” to “0”, so that the NMOS transistor NM3 and the PMOS transistor PM3 are turned on. As a result, the signal CMP2O Is output as the signal DETSOO. That is, in the period from when the signal PDRSO transitions until the delay time of the delay circuit VDLY2 elapses, the NMOS transistor NM3 and the PMOS transistor PM3 remain in the off state, and the signal CMP2O does not participate in the signal DETSOO. When the signal PDRSO transits from “1” to “0”, the signal INOUTSO transits from “1” to “0”. When the signal INOUTSO transitions from “1” to “0”, there is a state in which the voltage of the signal INOUTSO is higher than the threshold voltage VTL even when an output short circuit does not occur at the monitored external terminal. However, setting the delay time of the variable delay circuit VDLY2 to be longer than the transition time of the signal INOUTSO prevents the signal transition state of the monitoring target external terminal from being detected as the output short-circuit state of the monitoring target external terminal.

  Note that when the current drive capabilities of the input / output circuits IO1 to IO4 are different or the load capacitances of the external terminals P1 to P4 are different, the signal transition times of the external terminals P1 to P4 may be different. Since the delay times of the variable delay circuits VDLY1 and VDLY2 can be changed using PCDDLYCR, such a setting is made by setting the delay time control register PCDDLYCR in accordance with the signal transition time of the external terminal selected as the monitored external terminal. It can respond flexibly to cases.

  When the detection operation of the abnormality detection circuit PCDET is prohibited (when the signal PCDEO is set to “0”), or when the input / output circuit corresponding to the monitoring target external terminal functions as an input circuit ( When the signal DDRSO is set to “0”), since the signals AN2O and AN3O are set to “0”, the signals AN4O and AN5O are set to “0”, and the signals AN4OX and AN5OX are set to “1”. Is done. As a result, the NMOS transistors NM2 and NM3 and the PMOS transistors PM2 and PM3 are turned off, so that the signal DETSOO is not set to “1” in response to the signals CMP1O and CMP2O.

  Further, in the abnormality detection circuit PCDET, the detection operation of the abnormality detection circuit PCDET is permitted, and the input / output circuit corresponding to the monitored external terminal functions as an input circuit (the signal PCDEO is set to “1”). When the signal DDRSO is set to “0”), the input open state of the monitoring target external terminal is detected as follows. When the signal DDRSO is set to “0”, the signal NR2O is set to “1”, so that the switches SW1 and SW2 are turned on. As a result, the signal line INOUTSO (monitoring target external terminal) is connected. Pull-up resistor R1 and pull-down resistor R2 are connected. The pull-up resistor R1 and the pull-down resistor R2 have a large resistance value (for example, 100 kΩ), and a signal set to “0” (“1”) by an external circuit is input to the monitored external terminal. If the monitoring target external terminal is not in the input open state, the signal INOUTSO is set to “0” (“1”).

  When the signal INOUTSO is set to “0”, since the voltage of the signal INOUTSO is lower than the threshold voltages VTH and VTL, the signal CMP1O is set to “1” and the signal CMP2O is set to “0”. Therefore, the signal AN6O is set to “0”, and as a result, the signal DETSIO is set to “0”. When the signal INOUTSO is set to “1”, the voltage of the signal INOUTSO is higher than the threshold voltages VTH and VTL, so that the signal CMP1O is set to “0” and the signal CMP2O is set to “1”. Therefore, the signal AN6O is set to “0”, and as a result, the signal DETSIO is set to “0”.

  On the other hand, when no signal is input to the monitored external terminal by an external circuit due to disconnection or the like, and the monitored external terminal is in an input open state, due to the action of the pull-up resistor R1 and the pull-down resistor R2, The voltage of the signal INOUTSO is about ½ of the voltage of the power supply line VDD. At this time, since the voltage of the signal INOUTSO is lower than the threshold voltage VTH and higher than the threshold voltage VTL, the signals CMP1O and CMP2O are set to “1”. Therefore, the signal AN6O is set to “1”, and as a result, the signal DETSIO is set to “1”. Thereby, the input open state of the monitoring target external terminal is detected.

  Further, when the detection operation of the abnormality detection circuit PCDET is prohibited (when the signal PCDEO is set to “0”), or when the input / output circuit corresponding to the monitored external terminal functions as an output circuit ( When the signal DDRSO is set to “1”), since the signal NR2O is set to “0”, the signal DETSIO is not set to “1” according to the signals CMP1O and CMP2O.

  If the signal input to the monitored external terminal by the external circuit is not a signal fixed to “0” or a signal fixed to “1” but a signal accompanied by a transition, the signal transition state of the monitored external terminal May be detected as the input open state of the monitored external terminal. For example, by confirming the presence or absence of the input open state by software processing multiple times, the signal transition state of the monitored external terminal and the input open state may be detected. The state can be discriminated.

  As described above, in the abnormality detection circuit PCDET, since the threshold voltage generation circuit PCDVTG and the comparators CMP1 and CMP2 are shared by the output short circuit detection function and the input open detection function, the circuit area of the abnormality detection circuit PCDET can be reduced. As a result, the manufacturing cost can be reduced.

  FIG. 4 shows the threshold voltage generation circuit of FIG. The threshold voltage generation circuit PCDVTG includes a threshold voltage control register PCDVTCR, a decoder DEC2, a switch SW3, voltage dividing resistors RD1 to RD9, and selectors SEL4 and SEL5.

  The threshold voltage control register PCDVTCR is a register for variably specifying the voltage values of the threshold voltages VTH and VTL. For example, the threshold voltage control register PCDVTCR indicates one of the voltage values VTH1 to VTH4 (VTH4 <VTH3 <VTH2 <VTH1) as the voltage value of the threshold voltage VTH, and the voltage values VTL1 to VTL4 (VTL4 (VTL4) as the voltage values of the threshold voltage VTL. <VTL3 <VTL2 <VTL1) is set to a register value indicating any one of them. The signal VPCDVTCR is a signal indicating the set value of the threshold voltage control register PCDVTCR. The decoder DEC2 decodes the signal VPCDVTCR and outputs signals HSEL1 to HSEL4 and LSEL1 to LSEL4. Specifically, when the signal VPCDVTCR is set to a logical value indicating the voltage value VTH1 (VTH2, VTH3, VTH4) as the voltage value of the threshold voltage VTH, the decoder DEC2 outputs the signal HSEL1 (HSEL2, HSEL3, HSEL4). While setting to “1”, signals other than HSEL1 (HSEL2, HSEL3, HSEL4) in the signals HSEL1 to HSEL4 are set to “0”. The decoder DEC2 sets the signal LSEL1 (LSEL2, LSEL3, LSEL4) to “1” when the signal VPCDVTCR is set to a logical value indicating the voltage value VTL1 (VTL2, VTL3, VTL4) as the voltage value of the threshold voltage VTL. And signals other than LSEL1 (LSEL2, LSEL3, LSEL4) in the signals LSEL1 to LSEL4 are set to “0”.

  The switch SW3 and the voltage dividing resistors RD1 to RD9 are connected in series between the power supply line VDD and the ground line GND. The switch SW3 is turned off when the signal PCDEO is set to “0”, and is turned on when the signal PCDEO is set to “1”. The selector SEL4 includes switches SS41 to SS44. The switch SS41 (SS42, SS43, SS44) is connected between the connection node of the voltage dividing resistor RD1 (RD2, RD3, RD4) and the voltage dividing resistor RD2 (RD3, RD4, RD5) and the supply line of the threshold voltage VTH. ing. The switch SS41 (SS42, SS43, SS44) is turned off when the signal HSEL1 (HSEL2, HSEL3, HSEL4) is set to “0”, and the signal HSEL1 (HSEL2, HSEL3, HSEL4) is set to “1”. Turns on when set. The selector SEL5 includes switches SS51 to SS54. The switch SS51 (SS52, SS53, SS54) is connected between the connection node of the voltage dividing resistor RD5 (RD6, RD7, RD8) and the voltage dividing resistor RD6 (RD7, RD8, RD9) and the supply line of the threshold voltage VTL. ing. The switch SS51 (SS52, SS53, SS54) is turned off when the signal LSEL1 (LSEL2, LSEL3, LSEL4) is set to “0”, and the signal LSEL1 (LSEL2, LSEL3, LSEL4) is set to “1”. Turns on when set.

  In the threshold voltage generation circuit PCDVTG having such a configuration, when the threshold voltage control register PCDVTCR is set to a register value indicating the voltage value VTH1 (VTH2, VTH3, VTH4), the decoder DEC2 outputs the signal HSEL1 (HSEL2, HSEL3, HSEL4). As a result, the switch SS41 (SS42, SS43, SS44) is turned on in the selector SEL4, and the divided voltage VD1 (VD2, VD3, VD4) is output as the threshold voltage VTH. When the threshold voltage control register PCDVTCR is set to a register value indicating the voltage value VTL1 (VTL2, VTL3, VTL4), the signal LSEL1 (LSEL2, LSEL3, LSEL4) is set to “1” in the decoder DEC2, and as a result In the selector SEL5, the switch SS51 (SS52, SS53, SS54) is turned on, and the divided voltage VD5 (VD6, VD7, VD8) is output as the threshold voltage VTL. This makes it possible to supply threshold voltages VTLH and VTL having arbitrary voltage values. Further, there is a possibility that the voltage value corresponding to “1” or the voltage value corresponding to “0” of the input / output signals of the external terminals P1 to P4 may be different, but the threshold voltage VTH using the threshold voltage control register PCDVTCR, Since the voltage value of the VTL can be changed, the threshold voltage control register PCDVTCR is set in accordance with the voltage value corresponding to “1” or the voltage value corresponding to “0” of the input / output signal of the external terminal selected as the monitoring target external terminal. By setting, a stable detection operation of the abnormality detection circuit PCDET can be realized even in such a case.

  FIG. 5 shows the variable delay circuit of FIG. Since the variable delay circuits VDLY1 and VDLY2 have the same internal configuration, the variable delay circuit VDLY1 will be described here. The variable delay circuit VDLY1 includes a decoder DEC3, delay circuits DLY1 to DLY4, buffers BF1 to BF4, a decoder DEC2, and a selector SEL6.

  The delay circuit DLY1 delays the signal AN2O for a predetermined time and outputs it as the signal DLY1O. The buffer BF1 receives the signal DLY1O and outputs a signal BF1O. The delay circuit DLY2 delays the signal BF1O for a predetermined time and outputs it as the signal DLY2O. The buffer BF2 receives the signal DLY2O and outputs the signal BF2O. The delay circuit DLY3 delays the signal BF2O for a predetermined time and outputs it as a signal DLY3O. Buffer BF3 receives signal DLY3O and outputs signal BF3O. The delay circuit DLY4 delays the signal BF3O for a predetermined time and outputs it as the signal DLY4O. Buffer BF4 receives signal DLY4O and outputs signal BF4O. The decoder DEC3 decodes the signal VPCDDLYCR and outputs signals DSEL1 to DSEL4. Specifically, the decoder DEC3 sets the signal DSEL1 (DSEL2, DSEL3, DSEL4) to “1” when the signal VPCDDLYCR is set to a logical value indicating the delay time TD1 (TD2, TD3, TD4). In the signals DSEL1 to DSEL4, signals other than the signal DSEL1 (DSEL2, DSEL3, DSEL4) are set to “0”. When the signal DSEL1 (DSEL2, DSEL3, DSEL4) is set to “1”, the selector SEL6 outputs the signal BF1O (BF2O, BF3O, BF4O) as the signal VDLY1O. With such a configuration, the variable delay circuit VDLY1 in which the delay time is changed according to the set value (signal VPCDDLYCR) of the delay time control register PCDDLYCR can be easily realized.

  FIG. 6 shows the abnormality detection control circuit of FIG. The abnormality detection control circuit PCDCTL includes D-type flip-flops DFFa and DFFb and an interrupt signal generation circuit IRQSG. The D-type flip-flop DFF1 sets the signal DFF1O output from the output terminal Q to “0” when the signal PCDEO input to the clear terminal CL is set to “0”. In addition, when the signal PCDEO is set to “1”, the D-type flip-flop DFF1 has the input terminal D as the signal DETSOO input to the clock terminal CK transitions from “0” to “1”. The “1” fixed signal input to is input and output as a signal DFF1O. The D-type flip-flop DFF2 sets the signal DFF2O output from the output terminal Q to “0” when the signal PCDEO input to the clear terminal CL is set to “0”. In addition, when the signal PCDEO is set to “1”, the D-type flip-flop DFF2 has the input terminal D as the signal DETSIO input to the clock terminal CK transitions from “0” to “1”. The fixed signal “1” input to the signal DFF2O is taken in and output as a signal DFF2O.

  The interrupt signal generation circuit IRQSG includes an abnormality detection control register PCDCR. The abnormality detection control register PCDCR includes an abnormality detection permission bit PCDE, an output short circuit detection interrupt permission bit PCDOIE, an output short circuit detection interrupt factor flag PCDOIF, a real-time output short circuit detection flag DETSO, an input release detection interrupt permission bit PCDIIE, and an input release detection interrupt factor flag. PCDIIF and real-time input release detection flag DETSI are provided. The abnormality detection permission bit PCDE is set to “0” when the detection operation of the abnormality detection circuit PCDET is prohibited, and is set to “1” when the detection operation of the abnormality detection circuit PCDET is permitted. The signal PCDEO is a signal indicating the set value of the abnormality detection permission bit PCDE.

  The output short-circuit detection interrupt enable bit PCDOIE is set to “0” when the abnormality detection circuit PCDET prohibits the issuance of an interrupt request to the CPU accompanying the detection of the output short-circuit state of the external terminal to be monitored, and is monitored by the abnormality detection circuit PCDET. This is set to “1” when permitting the issuance of an interrupt request to the CPU accompanying the detection of the output short-circuit state of the target external terminal. The output short-circuit detection interrupt factor flag PCDOIF is set to “1” as the signal DDF1O transitions from “0” to “1”. Further, the output short-circuit detection interrupt factor flag PCDOIF can be initialized to “0” via the CPU write access. The real-time output short-circuit detection flag DSTSO is set to “0” when the signal DETSOO is set to “0”, and is set to “1” when the signal DETSOO is set to “1”.

  The input release detection interrupt permission bit PCDIIE is set to “0” when the issuance of an interrupt request to the CPU accompanying the detection of the input open state of the monitored external terminal by the abnormality detection circuit PCDET is set to “0”, and monitoring by the abnormality detection circuit PCDET Set to “1” when permitting the issuance of an interrupt request to the CPU accompanying detection of the input open state of the target external terminal. The input release detection interrupt factor flag PCDIIF is set to “1” as the signal DFF2O transitions from “0” to “1”. Further, the input release detection interrupt factor flag PCDIIF can be initialized to “0” through the CPU write access. The real-time input release detection flag DETSI is set to “0” when the signal DETSIO is set to “0”, and is set to “1” when the signal DETSIO is set to “1”.

  The interrupt generation circuit IRQSG sets the signal IRQPCD to “1” when the output short circuit detection interrupt factor flag PCDOIF is set to “1” while the output short circuit detection interrupt permission bit PCDOIE is set to “1”. (Issues an interrupt request to the CPU). The interrupt generation circuit IRQSG also sets the signal IRQPCD to “1” even when the input release detection interrupt factor flag PCDIIF is set to “1” while the input release detection interrupt permission bit PCDIIE is set to “1”. Set to "".

  According to such a configuration, it is easy to execute a desired process by a program when an output short circuit or an input open occurs at the monitoring target external terminal. In addition, since it is possible to confirm in real time whether there is an output short circuit or an input opening at the monitoring target external terminal, it is possible to easily identify the occurrence timing of the output short circuit or the input opening at the monitoring target external terminal.

  FIG. 7 shows switching control of the monitoring target external terminal. For example, the switching control of the monitoring target external terminal when the presence or absence of the output short circuit of the external terminals P1 to P3 is inspected in a time division manner will be described. For example, the signal transition time of the external terminal P1 is 0.1 us, the signal transition time of the external terminal P2 is 0.5 us, and the signal transition time of the external terminal P3 is 1.0 us.

  First, in order to check whether there is an output short circuit of the external terminal P1, the terminal selection control register DPSELCR is set to the register value of the external terminal P1, and the delay time control register PCDDLYCR is 0.1 us (corresponding to the delay time TD1). Set to a value. As a result, the external terminal P1 is selected as the monitoring target external terminal, and the detection operation of the abnormality detection circuit PCDET is performed on the external terminal P1. By setting the delay time of the variable delay circuits VDLY1 and VDLY2 to 0.1 us, the detection operation of the abnormality detection circuit PCDET is performed during the period from time t1 to time t2 (period in which the external terminal P1 is in the signal transition state). Is in a stopped state (disable).

  Next, at time t3, the signal PCDEO (abnormality detection permission bit PCDE of the abnormality detection control register PCDCR) is set to “0” to detect the abnormality detection circuit PCDET in order to check whether there is an output short circuit of the external terminal P2. After stopping the operation, the register value of the external terminal P2 is set in the terminal selection control register DPSELCR, and the register value of 0.5 us (corresponding to the delay time TD2) is set in the delay time control register PCDDLYCR. After the register setting is changed, the signal PCDEO is set to “1”, and the abnormality detection circuit PCDET can perform the detection operation after the delay time (0.5 us) of the variable delay circuits VDLY1 and VDLY2 elapses. Thereby, even when the external terminal P2 is in a signal transition state when the monitored external terminal is switched from the external terminal P1 to the external terminal P2, erroneous detection in the abnormality detection circuit PCDET can be prevented. When the delay time of the variable delay circuits VDLY1 and VDLY2 elapses after the signal PCDEO is set to “1”, the detection operation of the abnormality detection circuit PCDET is performed on the external terminal P2. By setting the delay time of the variable delay circuits VDLY1 and VDLY2 to 0.5 us, the detection operation of the abnormality detection circuit PCDET is performed in the period from time t4 to time t5 (period in which the external terminal P2 is in the signal transition state) Is stopped.

  At time t6, in order to check whether or not the output of the external terminal P3 is short-circuited, the signal PCDEO is set to “0” to stop the detection operation of the abnormality detection circuit PCDET, and then the terminal selection control register DPSELCR is set to the external terminal. A register value of P3 is set, and a register value of 1.0 us (corresponding to the delay time TD3) is set in the delay time control register PCDDLYCR. After the register setting is changed, the signal PCDEO is set to “1”, and the abnormality detection circuit PCDET can perform the detection operation after the delay time (1.0 us) of the variable delay circuits VDLY1 and VDLY2 elapses. However, in the example of FIG. 7, the external terminal P3 enters the signal transition state before the delay time of the variable delay circuits VDLY1 and VDLY2 elapses after the signal PCDEO is set to “1”, and from time t7 to time t8. In the period (period in which the external terminal P3 is in the signal transition state), the false detection prevention function for the signal transition state works, so the stop period of the detection operation of the abnormality detection circuit PCDET is extended and The detection operation is performed from time t8. Thereby, even when the external terminal P3 is in a signal transition state when the monitored external terminal is switched from the external terminal P2 to the external terminal P3, erroneous detection in the abnormality detection circuit PCDET can be prevented.

  Here, the usefulness of the output short circuit detection function by the combination of the terminal selection circuit DPSEL and the abnormality detection circuit PCDET in the microcontroller MCU will be described. The microcontroller MCU is equipped with a flash memory as a program storage memory. By utilizing the feature of flash memory that programs can be easily rewritten, external terminals P1 to P4 are monitored separately by four evaluation systems when debugging a program or checking system operation, and four evaluations are performed. Adopting a method of monitoring the external terminals P1 to P4 simultaneously in the entire system or a method of monitoring the external terminals P1 to P4 in a time-division manner while changing the monitored external terminals with one evaluation system Can do. Further, even when the microcontroller MCU is mass-produced as a product or the microcontroller MCU is being used by the user, the desired external terminals of the external terminals P1 to P4 can be rewritten by rewriting the flash memory program. The presence or absence of an output short circuit can be inspected. In other words, the output short-circuit detection function of the microcontroller MCU can be used as a debugging means in the field. Further, the number of external terminals that may cause an output short circuit among the external terminals of the microcontroller and the timing at which an output short circuit may occur at the external terminal of the microcontroller are often limited. In such a case, the microcontroller MCU performs time-division monitoring of the external terminals P1 to P4 while changing the monitored external terminals by software control in accordance with the system operation, so that the output short-circuit state of the external terminals P1 to P4 Can be detected. For example, by using the output short-circuit detection function in combination with the timer interrupt function, it becomes possible to periodically change the delay time of the monitored external terminal, the threshold voltages VTH and VTL, and the variable delay circuits VDLY1 and VDLY2. Thus, the usefulness of the output short circuit detection function by the combination of the terminal selection circuit DPSEL and the abnormality detection circuit PCDET in the microcontroller MCU is sufficient.

  Next, the usefulness of the input opening detection function by the combination of the terminal selection circuit DPSEL and the abnormality detection circuit PCDET in the microcontroller MCU will be described. In general, the open input detection function avoids a situation in which the microcontroller cannot operate normally when the connection between the external terminal and the external circuit is interrupted due to mechanical vibration or the like during the operation of the microcontroller. Therefore, it is used for system abnormality notification and self-diagnosis. For example, considering the case where the subsequent processing is executed after checking the presence or absence of input opening at the external terminal of the microcontroller at system startup, if an input opening detection circuit is provided for each external terminal, self-diagnosis is required. The time is short, but the microcontroller chip area is very large. In addition, when checking whether there is an open input at the external terminal of the microcontroller when starting up the system, it is not necessary to check whether there is an open input for multiple external terminals at the same time. There is no problem even if the presence or absence is checked in a time-sharing manner. Therefore, the usefulness of the input open detection function by the combination of the terminal selection circuit DPSEL and the abnormality detection circuit PCDET in the microcontroller MCU is also sufficient.

  In the first embodiment as described above, since the abnormality detection circuit PCDET is provided in common with the external terminals P1 to P4, the chip area of the microcontroller MCU can be reduced, and a significant cost reduction can be realized. Further, in the abnormality detection circuit PCDET, the threshold voltage generation circuit PCDVTG and the comparators CMP1 and CMP2 are shared by the output short circuit detection function and the input open detection function, so that the circuit area of the abnormality detection circuit PCDET can be reduced. As a result, the manufacturing cost can be suppressed.

  When the abnormality detection circuit PCDET detects the output short circuit state or the input open state of the monitoring target external terminal, it is selected as the monitoring target external terminal among the external terminals P1 to P4 by referring to the terminal selection control register DPSELCR. Since it is possible to determine which external terminal is present, for example, it is possible to execute appropriate processing using interrupt processing. Further, the threshold voltage control register PCDVTCR can be used to change the voltage values of the threshold voltages VTH and VTL. Therefore, the voltage value corresponding to “1” or the voltage value corresponding to “0” of the input / output signal of the monitored external terminal. By setting the threshold voltage control register PCDVTCR according to the above, even when the voltage value corresponding to “1” or the voltage value corresponding to “0” of the input / output signals of the external terminals P1 to P4 is different, the abnormality detection circuit PCDET A stable detection operation can be realized. In the threshold voltage generation circuit PCDVTG, when the detection operation of the abnormality detection circuit PCDET is prohibited, the switch SW3 is turned off, so that wasteful current consumption can be avoided.

  Further, in the abnormality detection circuit PCDET, the variable delay circuits VDLY1 and VDLY2 are provided, so that the signals CMP1O and CMP2O are not involved in the signal DETSOO during the period in which the monitoring target external terminal is in the signal transition state. It is possible to prevent the signal transition state of the terminal from being detected as the output short-circuit state of the monitored external terminal. Since the delay times of the variable delay circuits VDLY1 and VDLY2 can be changed using the delay time control register PCDDLYCR, the external terminal P1 is set by setting the delay time control register PCDDLYCR in accordance with the signal transition time of the monitored external terminal. Even when the signal transition times of .about.P4 are different, it can be flexibly dealt with.

  FIG. 8 shows a second embodiment of the present invention. In describing the second embodiment, the same reference numerals as those used in the first embodiment are used for the same elements as those described in the first embodiment, and a detailed description thereof is omitted. The microcontroller of the second embodiment is configured by replacing the abnormality detection circuit PCDET with the abnormality detection circuit PCDET 'in the microcontroller MCU of the first embodiment (FIG. 1).

  The abnormality detection circuit PCDET ′ includes AND circuits AN1 to AN3, AN6 to AN9, inverters IV3 and IV8, threshold voltage generation circuit PCDVTG, comparators CMP1 and CMP2, OR circuit OR1, NOR circuit NR2, switches SW1 and SW2, and bullup resistor R1. And a pull-down resistor R2. The AND circuit AN8 sets the signal AN8O to “0” regardless of the signal CMP1O when the signal AN2O is set to “0”, and outputs the signal CMP1O when the signal AN2O is set to “1”. Output as signal AN8O. The AND circuit AN9 sets the signal AN9O to “0” regardless of the signal CMP2O when the signal AN3O is set to “0”, and outputs the signal CMP2O when the signal AN3O is set to “1”. Output as signal AN9O. The OR circuit OR1 sets the signal DETSOO to “0” when both the signals AN8O and AN9O are set to “0”, and sets at least one of the signals AN8O and AN9O to “1”. The signal DETSOO is set to “1”.

  In the abnormality detection circuit PCDET ′ having such a configuration, the detection operation of the abnormality detection circuit PCDET ′ is permitted, and the input / output circuit corresponding to the monitored external terminal functions as an output circuit (the signal PCDEO is “ When the signal DDRSO is set to “1”), the output short-circuit state of the monitoring target external terminal is detected as follows. When the signal PDRSO is set to “0”, since the signal AN2O is set to “0”, the signal AN8O is set to “0” regardless of the signal CMP1O. Further, when the signal PDRSO is set to “0”, the signal PDRSOX is set to “1”, so that the signal AN3O is set to “1”, and as a result, the signal CMP2O is output as the signal AN9O. ing. Since the signal NR2O is set to “0”, the switches SW1 and SW2 are turned off. As a result, the pull-up resistor R1 and the pull-down resistor R2 are disconnected from the signal line INOUTSO. When an output short circuit occurs in the monitored external terminal in such a state, the signal CMP2O changes from “0” to “1” when the voltage of the signal INOUTSO rises from the voltage of the ground line GND and becomes higher than the threshold voltage VTL. Transition. For this reason, the signal AN9O changes from “0” to “1”, and as a result, the signal DETSOO changes from “0” to “1”. Thereby, the output short circuit state of the monitoring object external terminal is detected.

  On the other hand, when the signal PDRSO is set to “1”, since the signal PDRSOX is set to “0”, the signal AN3O is set to “0”. As a result, the signal AN9O is independent of the signal CMP2O. Is set to “0”. When the signal PDRSO is set to “1”, the signal AN2O is set to “1”, so that the signal CMP1O is output as the signal AN8O. If an output short circuit occurs in the monitored external terminal in such a state, the signal CMP1O changes from “0” to “1” when the voltage of the signal INOUTSO decreases from the voltage of the power supply line VDD and becomes lower than the threshold voltage VTH. Transition. For this reason, the signal AN8O changes from “0” to “1”, and as a result, the signal DETSOO changes from “0” to “1”. Thereby, the output short circuit state of the monitoring object external terminal is detected.

  Also, when the detection operation of the abnormality detection circuit PCDET ′ is prohibited (when the signal PCDEO is set to “0”), or when the input / output circuit corresponding to the monitored external terminal functions as an input circuit (When the signal DDRSO is set to “0”), since the signals AN2O and AN3O are set to “0”, the signal AN8O is set to “0” regardless of the signal CMP1O and is not related to the signal CMP2O. The signal AN9O is set to “0”. Therefore, the signal DETSOO is not set to “1” in response to the signals CMP1O and CMP2O.

  Even in the second embodiment as described above, the same effect as in the first embodiment can be obtained.

  FIG. 9 shows a third embodiment of the present invention. In the description of the third embodiment, the same reference numerals as those used in the first embodiment are used for the same elements as those described in the first embodiment, and detailed description thereof is omitted. The microcontroller of the third embodiment is configured by replacing the input / output circuit IO1 with the input / output circuit IO1 'in the microcontroller MCU of the first embodiment (FIG. 1).

  The input / output circuit IO1 'is configured by adding an OR circuit OR2 and a selector SEL7 in the input / output circuit IO1. The OR circuit OR2 outputs the signal DDR1O as the signal OR2O when the signal UARTOE is set to “0”, and outputs the signal OR2O to “0” regardless of the signal DDR1O when the signal UARTOE is set to “1”. Set to 1 ”. Instead of the signal DDR1O, the signal OR2O is input to the NAND circuit NA11 and the inverter IV11. Although not shown, the signal OR2O is input to the terminal selection circuit DPSEL instead of the signal DDR1O. The selector SEL7 outputs the signal PDR1O as the signal SEL7O when the signal UARTOE is set to “0”, and outputs the signal UARTO as the signal SEL7O when the signal UARTOE is set to “1”. Instead of the signal PDR1O, the signal SEL7O is input to the NAND circuit NA11 and the NOR circuit NR11. The signal UARTO is a UART transmission data signal. The signal UARTTO is a UART output enable signal, and is set to “0” when the output of the UART transmission data signal is prohibited, and is set to “1” when the output of the UART transmission data signal is permitted. .

  In the input / output circuit IO1 'configured as described above, when the signal UARTOE is set to "0", the signal DDR1O is output as the signal OR2O, and the signal PDR1O is output as the signal SEL71O. Therefore, the input / output circuit IO1 'functions as a general-purpose output circuit or a general-purpose input circuit, like the input / output circuit IO1. On the other hand, when the signal UARTOE is set to “1”, the signal OR2O is set to “1” and the signal UARTO is output as the signal SEL71O. Accordingly, the input / output circuit IO1 'functions as a UART output circuit.

  In the third embodiment as described above, the input / output circuit IO1 ′ having the UART output function in addition to the general-purpose input / output function is provided. However, even when the input / output circuit IO1 ′ functions as the UART output circuit. As in the case where the input / output circuit IO1 ′ functions as a general-purpose output circuit, the output short-circuit state of the external terminal P1 can be detected, and the same effect as in the first embodiment can be obtained.

  FIG. 10 shows a fourth embodiment of the present invention. In describing the fourth embodiment, the same reference numerals as those used in the first embodiment are used for the same elements as those described in the first embodiment, and a detailed description thereof is omitted. The microcontroller of the fourth embodiment is configured by replacing the input / output circuits IO1 to IO4 with the input / output circuits IO1 ″ to IO4 ″ in the microcontroller MCU of the first embodiment (FIG. 1).

  Input / output circuit IOi ”(i = 1, 2, 3, 4) is configured by adding NAND circuit NA2i and AND circuit ANAi in input / output circuit IOi. NAND circuit NA2i has signal PSELi of“ 0 ”. The signal NA2iO is set to “1” regardless of the signal DETSOO when it is set to “1”, and when the signal PSELi is set to “1”, the signal DETSOO is inverted and output as the signal NA2iO. ANAi sets the signal ANAiO to “0” regardless of the signal DDRiO when the signal NA2iO is set to “0”, and sets the signal DDRiO to the signal ANAiO when the signal NA2iO is set to “1”. The NAND circuit NA1i and the inverter INV1i receive the signal ANA instead of the signal DDRiO. O has been entered.

  In the input / output circuit IOi ”having such a configuration, if the external terminal Pi is not selected as the monitoring target external terminal in the terminal selection circuit DPSEL, the signal PSELi is set to“ 0 ”, so that the signal NA2iO is“ 1 ”. As a result, the signal DDRiO is output as the signal ANAiO. Therefore, the input / output circuit IOi ″ operates in the same manner as the input / output circuit IOi. On the other hand, if the external terminal Pi is selected as the monitoring target external terminal in the terminal selection circuit DPSEL, the signal PSELi is set to “1”, so that the signal NA2iO is set to a logical value opposite to that of the signal DETSOO. When the input / output circuit IOi ”functions as an output circuit (when the signal DDRiO is set to“ 1 ”), if the output short circuit does not occur at the external terminal Pi, the signal DETSOO is set to“ 0 ”. Therefore, the signal NA2iO is set to “1”, and as a result, the signal DDRiO is output as the signal ANAiO. Therefore, the input / output circuit IOi ″ operates in the same manner as the input / output circuit IOi. If an output short circuit has occurred at the external terminal Pi, the signal DETSOO is set to “1”, so that the signal NA2iO is set to “0”. As a result, the signal ANAiO is “ Set to 0 ". As a result, the signal NA1iO is set to “1” and the signal NR1iO is set to “0”, so that the PMOS transistor PM1i and the NMOS transistor NM1i are turned off, and the signal output operation of the input / output circuit IOi ”is performed. Stopped.

  In the fourth embodiment as described above, the same effect as in the first embodiment can be obtained, and when the output short-circuit state of the monitored external terminal is detected, the signal of the input / output circuit corresponding to the monitored external terminal The output operation can be automatically stopped (without software). As a result, it is possible to shorten the period during which the abnormal current flows through the transistor connected to the external terminal in which the output short-circuit state is detected. In other words, the period during which the transistor connected to the external terminal where the output short-circuit state is detected is damaged can be shortened.

The invention described in the above embodiments is organized and disclosed as an additional note below.
(Appendix 1)
A plurality of input / output circuits provided corresponding to a plurality of external terminals;
A monitoring target designating circuit that variably designates a monitoring target external terminal from among the plurality of external terminals;
When the input / output circuit corresponding to the monitored external terminal functions as an output circuit, the output short-circuit state of the monitored external terminal is detected, and the input / output circuit corresponding to the monitored external terminal functions as an input circuit. A semiconductor integrated circuit comprising: an abnormality detection circuit that detects an input open state of the monitoring target external terminal when the monitoring target external terminal is open.
(Appendix 2)
In the semiconductor integrated circuit according to attachment 1,
The abnormality detection circuit is
A reference voltage generation circuit for generating a reference voltage;
A voltage comparison circuit that compares the voltage of the monitored external terminal with the reference voltage;
A pull-up resistor and a pull-down resistor connected to the monitoring target external terminal when an input / output circuit corresponding to the monitoring target external terminal functions as an input circuit;
When an input / output circuit corresponding to the monitoring target external terminal functions as an output circuit, an output short circuit detection signal is output according to the comparison result of the voltage comparison circuit, and the input / output circuit corresponding to the monitoring target external terminal A semiconductor integrated circuit comprising: a detection signal output circuit that outputs an input open detection signal in accordance with a comparison result of the voltage comparison circuit when is functioning as an input circuit.
(Appendix 3)
In the semiconductor integrated circuit according to attachment 2,
The semiconductor integrated circuit, wherein the reference voltage generation circuit includes a voltage value designation circuit that variably designates a voltage value of the reference voltage.
(Appendix 4)
In the semiconductor integrated circuit according to attachment 2,
An abnormality detection control circuit for permitting / prohibiting the detection operation of the abnormality detection circuit;
The reference voltage generation circuit includes a voltage generation stop circuit that stops the voltage generation operation of the reference voltage generation circuit when the detection operation of the abnormality detection circuit is prohibited by the abnormality detection control circuit. Semiconductor integrated circuit.
(Appendix 5)
In the semiconductor integrated circuit according to attachment 1,
The abnormality detection circuit is
A time specification circuit for variably specifying the detection prohibition time;
A detection stop circuit for stopping the detection operation of the abnormality detection circuit in accordance with the signal transition of the monitored external terminal when the input / output circuit corresponding to the monitored external terminal functions as an output circuit; A semiconductor integrated circuit comprising:
(Appendix 6)
In the semiconductor integrated circuit according to attachment 1,
A semiconductor integrated circuit, comprising: an interrupt request issuing circuit for issuing an interrupt request to a central processing circuit in response to detection of an output short-circuit state or an input open state of the monitored external terminal by the abnormality detection circuit.
(Appendix 7)
In the semiconductor integrated circuit according to attachment 1,
The plurality of input / output circuits include an input / output circuit having a peripheral circuit output function in addition to a general-purpose input / output function.
(Appendix 8)
In the semiconductor integrated circuit according to attachment 1,
A semiconductor integrated circuit comprising: an output stop circuit that stops a signal output operation of an input / output circuit corresponding to the monitored external terminal in response to detection of an output short-circuit state of the monitored external terminal by the abnormality detection circuit circuit.

  As mentioned above, although this invention was demonstrated in detail, above-mentioned embodiment is only an example of this invention and this invention is not limited to these. Obviously, modifications can be made without departing from the scope of the present invention.

It is explanatory drawing which shows 1st Embodiment of this invention. It is explanatory drawing which shows the terminal selection circuit of FIG. It is explanatory drawing which shows the abnormality detection circuit of FIG. It is explanatory drawing which shows the threshold voltage generation circuit of FIG. It is explanatory drawing which shows the variable delay circuit of FIG. It is explanatory drawing which shows the abnormality detection control circuit of FIG. It is explanatory drawing which shows switching control of the monitoring object external terminal. It is explanatory drawing which shows 2nd Embodiment of this invention. It is explanatory drawing which shows 3rd Embodiment of this invention. It is explanatory drawing which shows 4th Embodiment of this invention. It is explanatory drawing which shows the prior art example (the 1) of the input / output port circuit of LSI. It is explanatory drawing which shows the prior art example (the 2) of the input-output port circuit of LSI. It is explanatory drawing which shows the prior art example (the 3) of the input-output port circuit of LSI. It is explanatory drawing which shows the prior art example (the 1) of the input port circuit of LSI. It is explanatory drawing which shows the prior art example (the 2) of the input port circuit of LSI.

Explanation of symbols

AN1 to AN9, ANA1 to ANA4 ... AND circuit; BF1 to BF4 ... buffer; CMP1, CPM2 ... comparator; DDR1 to DDR4 ... direction register; DEC1 to DEC3 ... decoder; Circuit: DPSEL ... Terminal selection circuit; DPSELCR ... Terminal selection control register; IO1-IO4, IO1 ', IO1 "-IO4" ... I / O circuit; IRQSG ... Interrupt signal generation circuit; IV11-IV14, IV21-IV24, IV3-IV8 Inverter; MCU; Microcontroller; NA11 to NA14, NA21 to NA24 NAND circuit; NM11 to NM14, NM2, NM3 NMOS transistor; NR11 to NR14, NR2 NOR circuit; R circuit; P1 to P4, external terminal; PCDCR, abnormality detection control register, PCDCTL, abnormality detection control circuit, PCDDLYCR, delay time control register, PCDET, PCDET ', abnormality detection circuit, PCDVTCR, threshold voltage control register, PCDVTG, threshold PDR1 to PDR4... Data register; PM11 to PM14, PM2, PM3... PMOS transistor; R1... Pullup resistor; R2 .. pulldown resistor; RD1 to RD9. , SS21 to SS24, SS31 to SS34, SS41 to SS44, SS51 to SS54, SW1 to SW3, switch; VDLY1, VDLY2, variable delay circuit

Claims (5)

A plurality of input / output circuits provided corresponding to a plurality of external terminals;
A monitoring target designating circuit that variably designates a monitoring target external terminal from among the plurality of external terminals;
When the input / output circuit corresponding to the monitored external terminal functions as an output circuit, the output short-circuit state of the monitored external terminal is detected, and the input / output circuit corresponding to the monitored external terminal functions as an input circuit. A semiconductor integrated circuit comprising: an abnormality detection circuit that detects an input open state of the monitoring target external terminal when the monitoring target external terminal is open. The semiconductor integrated circuit according to claim 1,
The abnormality detection circuit is
A reference voltage generation circuit for generating a reference voltage;
A voltage comparison circuit that compares the voltage of the monitored external terminal with the reference voltage;
A pull-up resistor and a pull-down resistor connected to the monitoring target external terminal when an input / output circuit corresponding to the monitoring target external terminal functions as an input circuit;
When the input / output circuit corresponding to the monitoring target external terminal functions as an output circuit, an output short circuit detection signal is output according to the comparison result of the voltage comparison circuit, and the input / output circuit corresponding to the monitoring target external terminal A semiconductor integrated circuit comprising: a detection signal output circuit that outputs an input open detection signal in accordance with a comparison result of the voltage comparison circuit when is functioning as an input circuit. The semiconductor integrated circuit according to claim 2,
The semiconductor integrated circuit, wherein the reference voltage generation circuit includes a voltage value designation circuit that variably designates a voltage value of the reference voltage. The semiconductor integrated circuit according to claim 2,
An abnormality detection control circuit for permitting / prohibiting the detection operation of the abnormality detection circuit;
The reference voltage generation circuit includes a voltage generation stop circuit that stops the voltage generation operation of the reference voltage generation circuit when the detection operation of the abnormality detection circuit is prohibited by the abnormality detection control circuit. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1,
The abnormality detection circuit is
A time specification circuit for variably specifying the detection prohibition time;
A detection stop circuit for stopping the detection operation of the abnormality detection circuit in accordance with the signal transition of the monitoring target external terminal when the input / output circuit corresponding to the monitoring target external terminal functions as an output circuit; A semiconductor integrated circuit comprising:

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