KR100242691B1 - Circuit for controlling count of a up/down counter - Google Patents

Abstract

The present invention relates to a count control circuit for controlling the count of an up / down counter using an upswitch and a downswitch composed of two contact switches. To this end, the circuit includes an up / down counter count control circuit for loading data applied from a central processing unit by a write control signal, the up-switch and down-switch having a two-contact switch structure; Result signal of logical combination of a predetermined first clock signal and a write control signal synchronized with a predetermined second clock signal transmitted through the first contact of the upswitch or downswitch according to on or off of upswitch and downswitch A clock providing unit for providing a clock signal of the up / down counter; The predetermined logic signal transmitted through the up switch or the second contact of the down switch according to the on / off of the up switch and the down switch is an up / down selection signal for selecting an up / down counter operation mode. It is configured to include a transmission path for transmission. Therefore, the user can freely control the operation mode of the up / down counter without involvement of the central processing unit to selectively control the value output from the up / down counter.

Description

Count control circuit of up / down counter {CIRCUIT FOR CONTROLLING COUNT OF A UP / DOWN COUNTER}

The present invention relates to an up / down counter, and more particularly to a count control circuit for controlling the count of an up / down counter.

In general, the up / down counter is used to increase or decrease a predetermined value loaded in a predetermined unit by an input clock signal and an up / down control signal, and is mainly used to variably provide a predetermined value.

The present invention provides a count control circuit for controlling the count of an up / down counter using an up switch and a down switch composed of two contact switches.

In order to achieve the above object, the count control circuit according to the present invention loads the data applied from the central processing unit by the write control signal in the number seven signaling protocol monitoring system (SPM) and stores the counted channel information for channel selection. A counting control circuit for up / down counters for outputting a signal, comprising: an upswitch and a downswitch having a two-contact switch structure; As a result of a logical combination of a write control signal synchronized with a predetermined first clock signal and a predetermined second clock signal transmitted through the first contact of the upswitch or downswitch according to the on or off of the upswitch and the downswitch, A clock providing unit for providing a clock signal of the up / down counter; The predetermined logic signal transmitted through the second switch of the upswitch or the downswitch according to the on / off of the upswitch and the downswitch is transmitted as an up / down selection signal for selecting the up / down counter operation mode. It characterized in that it comprises a transmission path for.

1 is a detailed circuit diagram of a count control circuit of an up / down counter according to the present invention.

* Explanation of symbols for main parts of the drawings

101: up switch 102: down switch

110: clock provider 113: logical AND device

115, 118: flip-flop 121: logical sum element

130: up / down counter

Hereinafter, an embodiment according to the present invention will be described in detail.

1 is a detailed circuit diagram of a count control circuit of an up / down counter according to the present invention, wherein a number seven signal and a link state monitoring system (NO. 7 Signaling Protocol Monitor) of an electronic switch are hereinafter described. It is an example of a count control circuit for a 32-bit up / down counter used for channel selection in SPM.

Referring to FIG. 1, the count control circuit according to the present invention includes an up / down counter 130, an up switch (UP-SW) 101 and a down switch (DOWN-SW) 102 controlled by a user, The clock of the up / down counter 130 is logically combined with a write control signal synchronized with a first clock signal of 2 Hz and a predetermined second clock signal transmitted through one contact of the up switch 101 and the down switch 102. The other side contact of the clock signal providing unit 110, the upswitch 101, and the downswitch 102 for providing the signal CLK, and the up / down selection signal input terminal U / of the up / down counter 130. It consists of a transmission path 140 connected between the D SEL.

The up and down switches 101 and 102 are configured as two contact switches. In the case of the up switch 101, when turned on by a user, the first and second switches 101 and 102 transmit a first clock signal to one contact point, and a resistor ( The 'low (GND) level' signal is transmitted through R3), and the 'low (GND) level' signal transmitted through the other side contact is transmitted through the transmission path 140 as described above. It is configured to be transmitted to the up / down select signal input terminal (U / D SEL). In the case of the down switch 102, when turned on by the user, one contact transmits a first clock signal, and the other contact transmits a 'high (+ 5V) level' signal through the resistor R4. The 'high level' signal transmitted through the other side contact is configured to be transmitted to the up / down selection signal input terminal U / D SEL of the up / down counter 130 through the transmission path 140 as described above. .

The clock signal providing unit 110 connects one input terminal to the above-described one side contact of the upswitch 101 and the other logical input element 113 and the AND to connect the other one input terminal to the above-described one side contact of the down switch 102. The signals output from the pull-up resistors R1 and R2 and the logical multiplication device 113 connected in series between one input terminal and + 5V of the device 113 and between the other input terminal and + 5V, respectively, are clock signals. Inverts the first D flip-flop 115 and the second clock signal which are cleared by the write control signal SCW of the up / down counter 130 and the second clock signal is inputted as the first clock signal 2 Hz. A second D flip-flop 118 using a signal transmitted through the inverter 117 and the inverter 117 as a clock signal and a write control signal SCW transmitted to the up / down counter 130 as an input signal; Logically sum the output signals Q of the first and second D flip-flops 115 and 118 as the clock signals of the up / down counter 130. It consists of the OR gate 121 for group.

In the case of the SPM device, the write control signal is provided from a CPU (Central Processing Unit, hereinafter abbreviated as CPU), which is provided through the input terminal D [0 ~ 4] of the up / down counter 130. (This signal may also be implemented as provided by the CPU described above.) It is provided for loading. Therefore, the write control signal is applied to the load input terminal LOAD of the up / down counter 130. When the up / down counter 130 is provided in the SPM device as described above, the output signal of the up / down counter 130 is provided as channel information CH0 to CH4 to be monitored.

The operation of the count control circuit shown in FIG. 1 will now be described.

First, when the upswitch 101 and the downswitch 102 are not controlled,

If a predetermined value (for example, channel 9 (01001) value) is transmitted from the CPU (not shown) via the local line D [0 ~ 4] and the write control signal is applied to the active high state, The write control signal is applied in the low state. Accordingly, the up / down counter 130 loads a predetermined value applied through the D [0 ~ 4] lines. In this case, the write control signal transmitted from the CPU (not shown) may be implemented without the inverter 131 in the active low state.

The predetermined value (channel 9 (01001)) loaded on the up / down counter 130 is output through the output terminals OUT [0 to 4] at the rising edge of the clock signal applied to the clock stage. At this time, the clock providing unit 110 provides a predetermined clock signal processed by the second clock signal of 20MHz to the clock terminal of the up / down counter 130. That is, since the signal applied through the input terminals D [0-4] at the rising edge of the clock signal is loaded as the output signal, the clock providing unit 110 is up / down during the enable period of the write control signal SCW. In order to make a rising (or rising) time point of the clock signal applied to the clock terminal of the counter 130, the second clock signal of 20 MHz applied is inverted through the inverter 117 to clock the second D flip-flop 118. It is applied in stage.

The second D flip-flop 118 transmits a write control signal applied at an active low level through an input terminal to one input terminal of the logic element 121 in synchronization with a clock signal of 20 MHz. The logic sum element 121 up / down the output signal of the second D flip-flop 118 applied through the line 120 regardless of the output signal of the first D flip-flop 115 applied through the line 119. Provided as a clock signal of the down counter 130. This is because the first D flip-flop 115 is cleared by the write control signal applied and outputs the low level signal through the output terminal Q.

The up / down counter 130 keeps the 01001 value on the output lines CH0 to CH4 as described above in synchronization with the signal output from the logic sum element 121.

In this state, when the up / down counter 130 maintains a predetermined value, assuming that the user presses the up switch 101, the operation is performed as follows.

First, when the up switch 101 is controlled to the on state, since the write mode control signal is kept in an inactive state, the output of the second D flip-flop 118 becomes 'low state' to the up / down counter 130. The provided clock signal becomes the output signal of the first D flip-flop 115. That is, when the up switch 101 is turned on, the 2 Hz clock signal is input to one input terminal of the logical multiplication device 113 through the line 111 while the down switch 102 is turned off. The high-level (+ 5V) signal through the pull-up resistor (R1) is applied through the logical multiplication device 113 outputs the signal applied through the line 111.

The output signal of the AND device 113 is transmitted as a clock signal of the first D flip-flop 115 through the line 114. The first D flip-flop 115 outputs a first clock signal applied through the input terminal D in synchronization with a clock signal applied through the line 114. By the operation of the first D flip-flop 115, the noise generated when the up or down switches 101 and 102 are controlled (on or off) is not transmitted, thereby stabilizing the transmitted first clock signal. The stabilized first clock signal is applied to the logical sum element 121 via the line 119, and the logic sum element 121 is applied through the line 119 because the signal applied through the line 120 is low level. The first clock signal is provided as a clock signal of the up / down counter 130.

Accordingly, the up / down counter 130 counts every rising edge of the applied first clock signal, and the up / down counter 130 performs the up count because the low level signal GND is transmitted through the transmission line 140. Since the first clock signal transmitted is 2 Hz, one count is performed every 0.5 seconds. When the period of the first clock signal to be transmitted is set differently, the aforementioned count period (0.5 seconds) is also different.

On the other hand, when the down switch 102 is turned on,

The high level (+ 5V) signal is provided through the resistor R4 to the up / down selection signal (U / D SEL) of the up / down counter 130 through the transmission path 140 and the up / down counter 130. Is set to the down count mode. In addition, since the high level (+ 5V) signal through the pull-up resistor R2 is applied to one input terminal of the logical multiplication device 110 through the transmission path 111, the signal applied through the transmission path 112 is a logical multiplication device ( 110 is an output signal. At this time, the output signal is also 2Hz. The output 2Hz signal is provided as a clock signal of the up / down counter 130 via the first D flip-flop 115 and the logic element 121 as in the case where the up switch 101 is in the on state. . The up / down counter 130 is down counted at the rising edge of the clock signal applied as described above.

As described above, the present invention allows the user to control the operation of the up / down counter freely using the up switch and the down switch, and the clock signal of the stable up / down counter using the D flip-flop. By providing a, the operation of the up / down counter can be efficiently operated, and when applied to the up / down counter provided in the SPM device, there is also an advantage that a channel can be selected without involvement of the CPU.

Claims (3)

In the count control circuit of the up / down counter for loading data applied from the central processing unit by the number seven signaling protocol monitoring system (SPM) by the write control signal, and outputting the counted value as channel information for channel selection, An upswitch and a downswitch having a two-contact switch structure; Logically combining the write control signal synchronized with the predetermined first clock signal and the predetermined second clock signal transmitted through the first contact of the upswitch or downswitch according to on or off of the upswitch and downswitch. A clock providing unit for providing a result signal as a clock signal of the up / down counter; An up / down to select an up or down operation mode of the up / down counter for a predetermined logic signal transmitted through the second contact of the upswitch or downswitch according to on or off of the upswitch and the downswitch; A count control circuit for up / down counters comprising a transmission path for transmitting as a selection signal. The method of claim 1, wherein the clock providing unit, A first logic element (113) for ANDing the signal applied through each transmission path connected to the first contact of the upswitch and downswitch; When the data applied from the CPU is loaded into the up / down counter, the first logic element 113 is cleared when the data is cleared by the write control signal and the up / down counter does not load the data. A first flip-flop 115 for stabilizing and transmitting the first clock signal in synchronization with a signal outputted through the first signal; A second flip-flop 118 for providing the write control signal synchronized with the second clock signal as a clock signal of the up / down counter when the up / down counter loads data transmitted from the central processing unit; ; And And a second logic element 121 for transmitting the sum of the output signals of the first flip-flop 115 and the second flip-flop 118 as a clock signal of the up / down counter. Count control circuit of up / down counter. 3. The first flip-flop of claim 2, wherein the first flip-flop is a D flip-flop having the first clock signal as an input signal and the output signal of the first logic element as a clock signal. A count control circuit for up / down counters comprising a D flip-flop having a second clock signal as a clock signal and the write control signal as an input signal.

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