KR900005307Y1 - Frequency alternating detective circuit - Google Patents

Frequency alternating detective circuit Download PDF

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Publication number
KR900005307Y1
KR900005307Y1 KR2019860020788U KR860020788U KR900005307Y1 KR 900005307 Y1 KR900005307 Y1 KR 900005307Y1 KR 2019860020788 U KR2019860020788 U KR 2019860020788U KR 860020788 U KR860020788 U KR 860020788U KR 900005307 Y1 KR900005307 Y1 KR 900005307Y1
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South Korea
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signal
gate
exclusive
frequency
delay unit
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KR2019860020788U
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Korean (ko)
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KR880013909U (en
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김태욱
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삼성전자주식회사
한형수
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Priority to KR2019860020788U priority Critical patent/KR900005307Y1/en
Publication of KR880013909U publication Critical patent/KR880013909U/en
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Publication of KR900005307Y1 publication Critical patent/KR900005307Y1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

내용 없음.No content.

Description

주파수 변화 감지회로Frequency change detection circuit

제1도는 본 고안의 블럭도.1 is a block diagram of the present invention.

제2도는 제1도의 주요부분에서의 파형도.2 is a waveform diagram of the main part of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

DL1, LD2: 지연기 G1,G2: 논리게이트DL 1 , LD 2 : Delay G 1 , G 2 : Logic Gate

R : 저항 BELL : 벨R: Resistance BELL: Bell

본 고안은 통신회로등의 클럭주파수가 변화하는 것을 감지하는 회로에 관한 것이다.The present invention relates to a circuit for detecting a change in clock frequency, such as communication circuits.

종래에는 통신회로와 기타 응용회로에서 클럭의 주파수가 회로 및 외부요인에 의해 변할 때, 시스템의 오동작이 발생하는 경우가 많다.Conventionally, malfunctions of the system often occur when the frequency of the clock is changed by circuits and external factors in communication circuits and other application circuits.

따라서, 본 고안의 목적은 상기한 결점을 해결하기 위해 안출한 것으로서, 클럭의 주파수를 모니터(Monitor)할 수 있는 회로를 제공하는 데 있다.Accordingly, an object of the present invention is to provide a circuit that can monitor the frequency of the clock, which is devised to solve the above drawbacks.

이하 첨부도면에 의거하여 본 고안의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제1도는 본 고안의 회로도로서, 입력단을 통해 인가되는 클럭신호(Cin)는 직접 익스클루시브 오아게이트(G1)의 한 입력단에 인가됨과 동시에 제1 지연기(DL1)를 통해 익스클루시브 오아게이트(G1)의 다른 입력단에 인가되고, 이 익스클루시브 오아게이트(G1)의 출력신호는 직접 노아게이트(G2)의 한 입력단에 인가됨과 동시에 제2 지연기(DL2)를 통해 노아게이트(G2)의 다른 입력단에 인가하며, 이 노아게이트(G2)에서 출력되는 신호는 저항(R1)을 거쳐 벨(BELL)을 구동시키도록 연결한다.FIG. 1 is a circuit diagram of the present invention, in which a clock signal Cin applied through an input terminal is directly applied to one input terminal of an exclusive oragate G 1 and is exclusive through a first delay DL 1 . Iowa gate is applied to the other input terminal of the (G 1), the exclusive Iowa gate (G 1) output signal as soon applied directly to one input terminal of the NOR gate (G 2) of the same time a second delay unit (DL 2) applied to the other input terminal of the NOR gate (G 2) and via a signal output from the NOR gate (G 2) is connected to drive a bell (bELL) via a resistor (R 1).

상기한 제1 지연기(DL1)는 정상클럭주기의에 해당하는 주기를 갖도록 하는 회로이고, 제2 지연기(DL2)는 정상클럭주기의에 해당하는 주기를 갖도록 하는 회로이다.The first delay unit DL 1 has a normal clock cycle. The second delay DL 2 is a circuit having a period corresponding to It is a circuit to have a period corresponding to.

제2도는 상기 구성을 갖는 주파수 변화 감지회로의 주요부분에서의 파형도로서, 본 고안의 동작설명과 병행하여 설명한다.2 is a waveform diagram of a main part of the frequency change detection circuit having the above configuration, which will be described in parallel with the operation description of the present invention.

입력되는 클럭신호(제2도의 A)는 제1 지연기(DL1)를 거쳐 지연시킨 신호 (제2도의 B)와 함께 익스클루시브 오아게이트(G1)에 인가되어서 배타적 논리합되고, 이 익스클루시브 오아게이트(G1)에서 출력된 신호(제2도의 C)는 제2 지연기(DL2)에서 지연시킨 신호(제2도의 D)와 함께 노아게이트(G2)에 입력된다.The input clock signal (A in FIG. 2) is applied to the exclusive OA gate G 1 together with the signal (B in FIG. 2) delayed through the first delay unit DL 1 and is exclusive logically summed. The signal (C in FIG. 2) output from the exclusive oragate G 1 is input to the noagate G 2 together with the signal (D in FIG. 2 ) delayed by the second delay unit DL 2 .

상기한 노아게이트(G2)에서 출력된 신호(제2도의 E)에서 펄스 신호가 나타나는 부분은 주파수가 정상 주파수보다배 이하 또는 2배 이상일 때 나타나므로 벨(BELL)을 구동시켜 경고음을 발생시키고, 펄스신호가 발생되지 않는 부분은 주파수가 정상주파수 보다배의 변화범위에서 나타나므로 경고음이 발생되지 않는다.The portion where the pulse signal appears in the signal output from the noble gate G 2 (E in FIG. 2) has a frequency that is higher than the normal frequency. It appears when it is less than 2 times or more than 2 times, so it generates a beep sound by driving the bell. It does not generate a warning sound because it appears in the ship's range of change.

이상과 같이 본고안에 의하면 전송시스템등의 클럭주파수가 변해서 일정범위를 벗어나면 경고음을 발생시켜 오동작을 방지한다.As described above, according to the present proposal, when the clock frequency of the transmission system changes and goes out of a certain range, a warning sound is generated to prevent malfunction.

Claims (1)

입력 클럭신호(Cin)는 제1 지연기(DL1)에 의해 1차 지연된 신호와 함께 배타적 논리합시키는 익스클루시브 오아게이트(G1)에 인가하고, 익스클루시브 오아게이트(G1)의 출력신호는 제2 지연기(DL2)에 의해 2차 지연된 신호와 함께 노아게이트(G2)에 인가하며, 이 노아게이트(G2)에서 출력되는 신호에 의해 벨(BELL)이 구동되도록 연결하여서, 정상주파수보다배 이상의 주파수변화가 발생할 때 경고음을 발생시키는 것을 특징으로 하는 주파수 변화감지회로.The input clock signal Cin is applied to the exclusive oragate G 1 which performs an exclusive OR with the signal delayed first by the first delay unit DL 1 , and outputs the exclusive ora gate G 1 . The signal is applied to the noar gate G 2 together with the second delayed signal by the second delay unit DL 2 , and connected so that the bell is driven by the signal output from the noa gate G 2 . , Than normal frequency A frequency change detection circuit, characterized in that for generating a warning sound when more than twice the frequency change occurs.
KR2019860020788U 1986-12-22 1986-12-22 Frequency alternating detective circuit KR900005307Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019860020788U KR900005307Y1 (en) 1986-12-22 1986-12-22 Frequency alternating detective circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019860020788U KR900005307Y1 (en) 1986-12-22 1986-12-22 Frequency alternating detective circuit

Publications (2)

Publication Number Publication Date
KR880013909U KR880013909U (en) 1988-08-31
KR900005307Y1 true KR900005307Y1 (en) 1990-06-15

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KR2019860020788U KR900005307Y1 (en) 1986-12-22 1986-12-22 Frequency alternating detective circuit

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KR880013909U (en) 1988-08-31

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