KR940001047Y1 - I / O duty monitor of digital module - Google Patents

I / O duty monitor of digital module Download PDF

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KR940001047Y1
KR940001047Y1 KR2019880018925U KR880018925U KR940001047Y1 KR 940001047 Y1 KR940001047 Y1 KR 940001047Y1 KR 2019880018925 U KR2019880018925 U KR 2019880018925U KR 880018925 U KR880018925 U KR 880018925U KR 940001047 Y1 KR940001047 Y1 KR 940001047Y1
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input
digital module
equipment
microprocessor
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KR900010585U (en
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권영민
김호
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금성계전 주식회사
백중영
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3003Monitoring arrangements specially adapted to the computing system or computing system component being monitored

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  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

내용 없음.No content.

Description

디지탈 모듈의 입출력 듀티 감시장치I / O duty monitor of digital module

제1도는 본 고안 입출력 듀티 감시장치의 회로도.1 is a circuit diagram of the input and output duty monitoring device of the present invention.

제2도의 (a) 내지 (h)는 제1도의 각부 파형도.(A)-(h) of FIG. 2 are each waveform diagram of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1,2 : 디코더 3,4 : 버퍼1,2: decoder 3,4: buffer

5 : 설정스위치 6 : 카운터부5: setting switch 6: counter

7 : 플립플롭 8 : 설비기기7: flip-flop 8: equipment

EXOR1 : 익스클루시브오아게이트EXOR1: Exclusive Oagate

본 고안은 마이크로프로세서의 출력을 이용하는 디지탈 모듈(Digital Module)에 관한 것으로, 특히 입, 출력 응답지연시간 요소를 하드웨어적으로 처리하여 입출력 듀티(Duty)를 감시하도록한 디지탈모듈의 입출력 듀티 감시장치에 관한 것이다.The present invention relates to a digital module that uses the output of a microprocessor, and more particularly, to an input / output duty monitoring device of a digital module configured to monitor input / output duty by hardware processing of input and output response delay time elements. It is about.

일반적으로 릴레이와 같은 디지탈신호를 이용하는 모듈은 마이크로프로세서를 통해 그의 입, 출력에 대한 동작을 확인하게 된다.In general, a module using a digital signal such as a relay checks the operation of its input and output through a microprocessor.

그런데 종래의 디지탈모듈의 입, 출력에 대한 확인은 소프트웨어적으로 프로그램루틴을통해 처리되었으나 조작후 감시타이머에 대한 기동을 처리하므로 프로그램의 기능이 복잡해지고 제약되는 결함이 있었다.By the way, the confirmation of the input and output of the conventional digital module was processed through the program routine in software, but since the operation of the monitoring timer after the operation was processed, the function of the program was complicated and limited.

본 고안은 이와같은 종래의 결함을 감안하여 디지탈 모듈의 입, 출력에 대한 확인을 하드웨어적으로 처리하여, 이상발생시에만 메인프로그램에 전송함으로써 마이크로프로세서의 역할을 간소화할 뿐아니라 조작신호에 대한 신뢰성을 갖도록한 디지탈 모듈의 입출력 듀티 감시장치를 안출한 것으로, 이를 첨부한 도면에 의해 상세히 설명하면 다음과 같다.In consideration of such a conventional defect, the present invention processes the input and output confirmation of the digital module in hardware and transmits it to the main program only when an error occurs, thereby simplifying the role of the microprocessor and improving reliability of the operation signal. An input / output duty monitoring device of a digital module having a design is described, which will be described in detail with reference to the accompanying drawings.

제1도는 본 고안 입출력 듀티감시장치의 회로도로서 이에 도시한 바와같이, 마이크로프로세서로 부터 인가되는 어드레스가 디코더(1) (2)를 통해 버퍼(3) (4)를 인에이블하고, 시스템 클럭으로 구동되는 카운터부(6)의 채널을 로드하게하며, 상기 마이크로프로세서로 부터 인가되는 데이터가 상기 버퍼(3)를 통해 설비기기(8)를 구동하게 하며, 상기 설비기기(8)의 입, 출력이 익스클루시브오아게이트(EXORT1)를 통해 상기 카운터부(6)를 인에이블한후 설정스위치(5)의 출력에 따라 플립플롭(7)를 인에이블하고, 상기 버퍼(4)를 통해 마이크로프로세서에 확인데이터를 제공하게 구성한 것으로, 상기 설비기기(8)는 n개의 입출력을 갖도록한 것이다.FIG. 1 is a circuit diagram of an input / output duty monitoring apparatus of the present invention, as shown in FIG. 1, in which an address applied from a microprocessor enables buffers 3 and 4 through decoders 1 and 2 to the system clock. It loads the channel of the driven counter section 6, and the data applied from the microprocessor drives the equipment 8 through the buffer 3, the input and output of the equipment 8 After enabling the counter unit 6 through the exclusive ore gate EXORT1, the flip-flop 7 is enabled in accordance with the output of the setting switch 5, and the microprocessor is opened through the buffer 4. The equipment 8 is configured to have n inputs and outputs.

여기서 상기 플립플롭(7)은 D 플립플롭으로서 입력측(D)에 저항(R1)을 통해 전원(V+)이 항상 인가되어 고전위입력상태로 설정되게 설계된 것이다.Herein, the flip-flop 7 is a D flip-flop and is designed to be set to a high potential input state by always applying power V + to the input side D through the resistor R1.

제2도의 (a) 내지 (h)는 제1도의 각부파형도로서 이에 도시한 바와같이, (a)는 시스템클럭신호, (b-d)는 설비기기(8)의 입, 출력에 대한 디지탈신호, (e) (f)는 익스클루시브오아게이트(EXOR1)의 출력신호, (g)는 카운터부(8)의 출력신호, (h)는 카운터부(6)의 체널로드신호를 나타낸 것이다.(A) to (h) of FIG. 2 are angular waveform diagrams of FIG. 1, as shown in (a), a system clock signal, (bd) a digital signal for input and output of the equipment 8, (e) (f) shows the output signal of the exclusive oar gate EXOR1, (g) shows the output signal of the counter section 8, and (h) shows the channel load signal of the counter section 6.

이와같이 구성된 본 고안의 작용효과를 설명하면 다음과 같다.Referring to the effect of the present invention configured as described above are as follows.

마이크로프로세서로부터 출력되는 어드레스가 디코더(1)를 통해 출력(Q1) (Q2)으로 디코더(2)를 인에이블함과 아울러 버퍼(3) (4)를 인에이블함에 따라 마이크로프로세서로부터 출력되는 데이타가 상기 버퍼(3)를 통해 설비기기(8)에 인가되어 이를 구동하며, 이때 마이크로프로세서로부터 출력되는 어드레스가 디코더(2)를 통해 제2도(h)에 도시한 바와같이 펄스로 카운터부(6)를 로드하여 카운터에 대한 채널을 선택한다.As the address output from the microprocessor enables the decoder 2 through the decoder 1 to the outputs Q1 and Q2, as well as enabling the buffers 3 and 4, the data output from the microprocessor It is applied to the equipment 8 through the buffer 3 and drives it. At this time, the address outputted from the microprocessor is passed through the decoder 2 as shown in FIG. ) To select the channel for the counter.

여기서 설비기기(8)에 입력되는 디지탈신호가 제2도(b)에 도시한 바와같고, 이에 대한 설비기기(8)의 출력파형이 제2도(c) (d)에 도시한 바와같다고 하면, 익스클루시브오아게이트(EXOR1)를 통과한 설비기기(8)의 입, 출력에 대한 변화신호가 제2도(e) (f)에 도시한 바와같이되어 카운터부(6)를 인에이블시킨다.Here, suppose that the digital signal input to the equipment 8 is as shown in Fig. 2 (b), and the output waveform of the equipment 8 is as shown in Fig. 2 (c) (d). The change signal for the input and output of the equipment 8 that has passed through the exclusive oar gate EXOR1 is enabled as shown in Fig. 2 (e) and (f) to enable the counter section 6. .

이와같이하여 카운터부(6)는 제2도(a)에 도시한 바와같은 시스템클럭신호로 구동되고, 설정스위치(5)의 설정시간을 카운팅한후 제2도(g)에 도시한 바와같은 파형을 출력하게 되며, 이때 설정스위치(5)의 출력을 시간(3T)으로 설정하였기 때문에 제2도(f)에 도시한 바와같은 인에이블신호의 경우에만 카운팅되어 제2도(g)에 도시한 바와같은 파형이 출력된 것이다.In this way, the counter 6 is driven by a system clock signal as shown in Fig. 2A, and after counting the setting time of the setting switch 5, the waveform as shown in Fig. 2G is shown. In this case, since the output of the setting switch 5 is set to the time 3T, only the enable signal as shown in FIG. 2 (f) is counted and shown in FIG. The waveform as shown is output.

여기서 설정스위치(5)의 출력은 마이크로프로세서로부터 설비기기(8)에 보내지는 출력에이타를 받아서 구동할 수 있는시간을 파악하여 설정한 것이다.Here, the output of the setting switch 5 is set by grasping the time that can be driven by receiving an output sent from the microprocessor to the equipment 8.

이와동시에 상기 제2도(g)에 도시한 바와같은 카운터부(6)의 출력이 플립플롭(7)을 인에이블하며, 이때 고전위로된 플립플롭(7)의 출력이 버퍼(4)를 통해 마이크로프로세서의 데이타버스에 인가되어 전달됨으로써 설비기기(8)의 입, 출력파형의 상이함이 인식되는 것이다.At the same time, the output of the counter part 6 as shown in FIG. 2 (g) enables the flip-flop 7, wherein the output of the flip-flop 7 with high potential is passed through the buffer 4. The difference between the input and output waveforms of the equipment 8 is recognized by being applied to the data bus of the microprocessor.

이상에서 상세히 설명한 바와같이 본 고안은 설비기기에 대하여 하드웨어적으로 감시한후 이상의 발생시에만 메인프로그램에 전송하므로 마이크로프로세서의 역할을 축소할 수 있을 뿐아니라 조작신호에 대한 신뢰성을 향상시킬 수 있는 효과가 있다.As described in detail above, the present invention can not only reduce the role of the microprocessor but also improve the reliability of the operation signal since it is transmitted to the main program only when an abnormality occurs after monitoring the hardware of the equipment. have.

Claims (1)

디지탈신호를 이용하는 디지탈 모듈에 있어서, 어드레스 디코더(1) (2)를 통해 버퍼(3) (4)를 인에이블함과 아울러 시스템클럭으로 구동하는 카운터부(6)의 채널을 로드하고, 데이타가 상기 버퍼(3)를 통해 설비기기(8)를 구동하며, 이의 입출력이 익스클루시브오아게이트(EXOR1)를 통해 상기 카운터부(6)를 인에이블한후 설정스위치(5)의 출력에 따라 플립플롭(7)를 구동하고, 상기 버퍼(4)를 통해 상기 데이타라인에 인가되게하여, 감시되는 것을 특징으로 하는 디지탈 모듈의 입출력 듀티감시장치.In the digital module using the digital signal, the buffers (3) and (4) are enabled through the address decoder (1) and (2), and the channel of the counter section (6) driven by the system clock is loaded, and the data is stored. The equipment 8 is driven through the buffer 3, and the input / output thereof enables the counter unit 6 through an exclusive ore gate EXOR1 and then flips according to the output of the setting switch 5. An input / output duty monitoring device for a digital module, characterized in that for driving a flop (7) and being applied to the data line via the buffer (4).
KR2019880018925U 1988-11-22 1988-11-22 I / O duty monitor of digital module Expired - Fee Related KR940001047Y1 (en)

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