KR870002213Y1 - Arrangement for starting electric motor - Google Patents

Arrangement for starting electric motor Download PDF

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KR870002213Y1
KR870002213Y1 KR2019840014365U KR840014365U KR870002213Y1 KR 870002213 Y1 KR870002213 Y1 KR 870002213Y1 KR 2019840014365 U KR2019840014365 U KR 2019840014365U KR 840014365 U KR840014365 U KR 840014365U KR 870002213 Y1 KR870002213 Y1 KR 870002213Y1
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terminal
output
signal
exor
flip
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KR2019840014365U
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KR860008908U (en
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김근묵
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주식회사 금성사
허신구
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P8/00—Arrangements for controlling dynamo-electric motors rotating step by step
    • H02P8/14—Arrangements for controlling speed or speed and torque
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Control Of Stepping Motors (AREA)

Abstract

내용 없음.No content.

Description

스텝핑 모우터 등속 구동시 입력신호 발생회로Input signal generation circuit during stepping motor constant speed driving

제1도는 본 고안의 회로도.1 is a circuit diagram of the present invention.

제2도는 제1도의 출력진리치표.2 is an output truth table of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 스텝핑모우터구동회로부 AND1: 앤드게이트1: Stepping motor driving circuit part AND 1 : And gate

EXOR1-EXOR4: 익스클루시브아게이트EXOR 1 -EXOR 4 : Exclusive Agate

FF1-FF2: 플립플롭 B1-B4: 버퍼FF 1 -FF 2 : Flip-flop B 1 -B 4 : Buffer

L1-L4: 스텝핑모우터코일L 1 -L 4 : Stepping motor coil

본 고안은 스텝핑 모우터(Stepping Motor) 구동신호를 하드웨어적으로 발생시킬 수 있게 한 스텝핑 모우터 등속구동시 입력신호 발생회로에 관한 것이다.The present invention relates to an input signal generation circuit during stepping motor constant speed driving which can generate a stepping motor driving signal in hardware.

종래에 있어서는 마이크로 프로세서의 자체내에서 시간지연 회로와 타이머를 사용하여 스텝핑 모우터 구동신호를 직접 발생시키게 되어 있으므로 마이크로 프로세서에서의 점유시간이 길어지게 되고, 이에 따라 스텝핑 모우터를 사용하는 타이프 라이터나 프린터의 몇개의 구동원을 마이크로 프로세서로 동시 제어하는데 문제점이 발생되었다.In the related art, the time delay circuit and the timer are used to directly generate a stepping motor driving signal in the microprocessor itself, so that the occupancy time of the microprocessor becomes long, and thus a typewriter using a stepping motor or the like can be used. There has been a problem in controlling several driving sources of a printer simultaneously with a microprocessor.

본 고안은 이러한 종래의 해결하기 위하여 클럭 신호 및 방향지시신호에 의해 하드웨어적으로 스텝핑 모우터 구동신호를 발생하여 마이크로 프로세서의 점유시간을 줄여줄 수 있게 안출한 것으로, 이를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.The present invention has been made to reduce the occupancy time of the microprocessor by generating a stepping motor driving signal in hardware by the clock signal and the direction indication signal in order to solve such a conventional, in detail with reference to the accompanying drawings The explanation is as follows.

제1도는 본 고안의 스텝핑 모우터 동속구동시 입력신호 발생회로도로서 이에 도시한 바와 같이, 방향 지시신호단자(DS)를 익스쿨루시브오아게이트(EXOR1-EXOR4)의 일측입력 단자에 공통접속하여 그의 출력단자를 플립플롭(FF1), (FF2)의 입력단자(J1), (K1), (J2), (K2)에 각각 접속하고, 클럭신호단자(CK) 및 인에이블신호단자(EN)를 앤드게이트(AND1)의 입력단자에 접속하여 그의 출력단자를 플립플롭(FF1), (FF2)의 클럭단자(CK1), (CK2)에 공통접속하여, 그의 출력단자(Q1), (Q2),를 익스클루시브오아게이트(EXOR3), (EXOR4), (EXOR1)의 타측 입력단자에 각각 접속함과 아울러 버퍼(B1), (B2), (B3), (B4)를 각각 통하여 스텝핑 모우터 구동회로부(1)의 입력단자(I1), (I2), (I3), (I4)에 각각 접속하고, 이 스텝핑 모우터구동회로부(1)의 출력단자(O1), (O2), (O3), (O4)를 스텝핑모우터코일(L1), (L3), (L4)에 접속하여 구성한 것으로, 도면의 설명중 미설명부호 Vcc는 전원단자이고, R1-R4는 풀업저항이다.1 is an input signal generation circuit diagram of stepping motor co-operation according to the present invention. As shown in FIG. 1, the direction indication signal terminal DS is common to one input terminal of the exclusive oar gates EXOR 1 to EXOR 4 . Connect the output terminal thereof to the input terminals J 1 , K 1 , J 2 , and K 2 of the flip-flop FF 1 and FF 2 , respectively, and the clock signal terminal CK And the enable signal terminal EN is connected to the input terminal of the AND gate AND 1 , and its output terminal is common to the clock terminals CK 1 and CK 2 of the flip-flops FF 1 and FF 2 . Connected to the output terminals Q 1 , Q 2 , Is connected to the other input terminal of the exclusive oragate (EXOR 3 ), (EXOR 4 ), (EXOR 1 ), respectively, and the buffers (B 1 ), (B 2 ), (B 3 ), (B 4 ) Are respectively connected to the input terminals I 1 , I 2 , I 3 , and I 4 of the stepping motor driving circuit section 1 through the output terminals of the stepping motor driving circuit section 1, respectively. (O 1 ), (O 2 ), (O 3 ), (O 4 ) are connected to the stepping motor coils (L 1 ), (L 3 ), (L 4 ) For reference, in the description of the drawings, reference numeral Vcc denotes a power supply terminal, and R 1 -R 4 denote pull-up resistors.

이와같이 구성된 본 고안의 작용효과를 상세히 설명하면 다음과 같다.Referring to the effects of the present invention configured in this way in detail as follows.

전원단자(Vcc)에 전원이 인가되고, 인에이블신호단자(EN)에 인에이블신호가 인가된 상태에서 클럭신호단자(CK)에 클럭신호가 인가되면, 그 클럭신호는 앤드게이트(AND1)를 통하여 플립플롭(FF1), (FF2)의 클럭단자(CK1), (CK2)에 인가되므로 그의 출력단자(Q1), (Q2)에 저전위신호가 출력되어 익스클루시브오아게이트(EXOR3), (EXOR2)의 타측 입력단자에 인가되고, 그의 출력단자에 고전위 신호가 출력되어 익스클루시브오아게이트(EXOR4), (EXOR1)의 타측입력단자에 인가된다. 따라서, 이때 방향지시신호단자(DS)에 정방향신호인 고전위신호가 인가되고 있으면 익스클루시브오아게이트(EXOR1), (EXOR3)의 출력단자에 고전위신호가 출력되어 플립플롭(FF1), (FF2)의 입력단자(K1), (J2)에 인가되고, 익스클루시브오아게이트(EYOR2), (EXOR4)의 출력단자에 저전위신호가 출력되어 플립플롭(FF1), (FF2)의 입력단자(J1), (K2)에 인가된다. 따라서, 클럭신호단자(CK)에 클럭신호가 다시 인가될 때 플립플롭(FF1)은 크리어 상태로 되어 그의 출력단자(Q1),에는 계속 저전위 및 고전위 신호가 각각 출력되고, 플립플롭(FF2)은 세트상태로 되어 그의 출력단자(Q1),에 고전위 및 저전위신호가 각각 출력된다.When power is applied to the power supply terminal Vcc and a clock signal is applied to the clock signal terminal CK while the enable signal is applied to the enable signal terminal EN, the clock signal is an AND gate AND 1 . Is applied to the clock terminals CK 1 and CK 2 of the flip-flops FF 1 and FF 2 , so that a low potential signal is output to the output terminals Q 1 and Q 2 . It is applied to the other input terminal of OA gate (EXOR 3 ), (EXOR 2 ), and its output terminal The high potential signal is output to the other input terminal of the exclusive OR gates (EXOR 4 ) and (EXOR 1 ). Therefore, if a high potential signal, which is a forward signal, is applied to the direction indication signal terminal DS, a high potential signal is output to the output terminals of the exclusive ogates EXOR 1 and EXOR 3 and flip-flop FF 1. ) And (FF 2 ) are applied to the input terminals (K 1 ) and (J 2 ), and the low-potential signal is output to the output terminals of the exclusive OA gates (EYOR 2 ) and (EXOR 4 ) to provide a flip-flop (FF). 1), it is applied to the input terminal (J 1), (K 2 ) of (FF 2). Therefore, when the clock signal is applied to the clock signal terminal CK again, the flip-flop FF 1 is in a cree state and its output terminal Q 1 , The low and high potential signals are continuously output, and the flip-flop FF 2 is set to its output terminal Q 1 , The high potential and low potential signals are respectively output to.

이와같이 플립플롭(FF1), (FF2)의 출력단자(Q1),에서 출력된 저전위신호는 익스클루시브오아게이트(EXOR3), (EXOR1)의 입력단자에 인가되므로 그 플립플롭(FF1), (FF2)의 입력단자(J1), (J2)에 고전위 신호가 인가되고, 의 출력단자에서 출력된 고전위 신호는 익스클루시브오아게이트(EXOR4), (EXOR2)의 타식입력단자에 인가되므로 그 플립플롭(FF1), (FF2)의 입력단자(K1), (K2)에 저전위 신호가 인가된다.In this way, the output terminals (Q 1 ) of the flip-flops (FF 1 ) and (FF 2 ), The low-potential signal output from is applied to the input terminals of the exclusive OR gates (EXOR 3 ) and (EXOR 1 ), so the input terminals (J 1 ) and (J 2 ) of the flip-flops (FF 1 ) and (FF 2 ) are A high potential signal is applied to) and the output terminal of The high potential signal output from is applied to the other input terminal of the exclusive oar gates (EXOR 4 ) and (EXOR 2 ), so the input terminals (K 1 ) and (K) of the flip-flops (FF 1 ) and (FF 2 ) are 2 ) a low potential signal is applied.

따라서, 다시 클럭신호단자(CK)에 클럭신호가 인가될 때 플립플롭(FF1), (FF2)은 세트상태로 그들의 출력단자(Q1), (Q2)에 고전위 신호가 출력되고, 출력단자에 저전위 신호가 출력되며, 마찬가지로, 이후 다시 클럭신호단자(CK)에 클럭신호가 인가될 때 플립플롭(FF1)은 세트상태로 되고 플립플롭(FF2)은 크리어 상태로 되어 그의 출력단자(Q1),에 고전위 신호가 출력되고, 출력단자, (Q2)에 저전위 신호가 출력된다.Therefore, when the clock signal is applied to the clock signal terminal CK again, the high-floor signals are output to their output terminals Q 1 and Q 2 in the set state of the flip-flops FF 1 and FF 2 . , Output terminal The low-potential signal is outputted to the output terminal. Similarly, when the clock signal is applied to the clock signal terminal CK again, the flip-flop FF 1 is set and the flip-flop FF 2 is set to the cree state. (Q 1 ), High potential signal is output to output terminal The low potential signal is output to (Q 2 ).

이상의 동작관계를 진리치표로 나타내면 제2도에 도시한 바와 같이 된다.The above operation relations are represented by the truth table as shown in FIG.

한편, 상기와 같이 플립플롭(FF1), (FF2)의 출력단자(Q1), (Q2),에서 출력된 신호는 버퍼(B1), (B2), (B3), (B4)를 각각 통하여 스텝핑모우터구동회로부(1)의 입력단자(I1), (I2), (I3), (I4)에 인가되므로 그에 대응되게 그의 출력단자(O1), (O2), (O3), (O4) 중 2개에 저전위 신호가 출력되어 스텝핑모우터코일(L1-L4)에 전류가 흐를 수 있게 한다.On the other hand, the flip-flop (FF 1), the output terminal (Q 1) of (FF 2), (Q 2 ) as above, The signals output from the input terminals (I 1 ), (I 2 ), (of the stepping motor driving circuit unit 1 through the buffers (B 1 ), (B 2 ), (B 3 ), (B 4 ) respectively. I 3 ) and (I 4 ) are applied to the output terminal (O 1 ), (O 2 ), (O 3 ), (O 4 ) corresponding to the low potential signal is output to the stepping motor coil Allow current to flow in (L 1- L 4 ).

즉, 플립플롭(FF1), (FF2)의 출력단자(Q1), (Q2)에 저전위신호가 출력되고, 출력단자에 고전위신호가 출력된 상태에서는 스텝핑모우터구동회로부(1)의 출력단자(O1), (O2)에는 저전위신호가 출력되고 출력단자(O3), (O4)에는 고전위 신호가 출력되어 스텝핑모우터코일(L1), (L2)에만 전원단자(Vcc)의 전원이 흐르게 되고, 이후 클럭신호단자(CK)에 클럭신호가 인가되어 플립플롭(FF1), (FF2)의 출력단자(Q1),에 저전위 신호가 출력되고 출력단자, (Q2)에 고전위신호가 출력된 상태에서는 스텝핑모우터구동회로부(1)의 출력단자(O1), (O4)에만 저전위신호가 출력되어 스텝핑모우터코일(L1), (L4)에 전원단자(Vcc)의 전원이 흐르게 된다.That is, a low potential signal is output to the output terminals Q 1 and Q 2 of the flip-flops FF 1 and FF 2 , and the output terminal is output. When the high potential signal is output to the output terminal (O 1 ), (O 2 ) of the stepping motor drive circuit (1), the low potential signal is output, and the output terminal (O 3 ), (O 4 ) high potential The signal is outputted so that the power of the power supply terminal Vcc flows only to the stepping motor coils L 1 and L 2 , and then a clock signal is applied to the clock signal terminal CK so that the flip-flops FF 1 and ( FF 2 ) output terminal (Q 1 ), Low potential signal is output to output terminal When the high potential signal is output to (Q 2 ), the low potential signal is output only to the output terminals (O 1 ) and (O 4 ) of the stepping motor driving circuit unit 1 so that the stepping motor coil (L 1 ), The power of the power supply terminal Vcc flows to (L 4 ).

결과적으로, 방항지시신호단자(DS)에 정방항지시신호인 고전위신호가 인가된 상태에서 클럭신호단자(CK)에 클럭신호가 인가됨에 따라 스텝핑모우터코일(L1-L4)에는 L2, L1→ L1, L4→ L4, L3→ L3, L2→ L2, L1순서로 전류가 흐르게 되어 스텝핑모우터는 정방향으로 한 스텝씩 구동한다.As a result, as the clock signal is applied to the clock signal terminal CK in the state where the high potential signal, which is the forward direction instruction signal, is applied to the command signal terminal DS, the stepping motor coils L 1 to L 4 have L values. 2 , L 1 → L 1 , L 4 → L 4 , L 3 → L 3 , L 2 → L 2 , L 1 , so the current flows in the order of stepping motor.

그리고, 방향신호단자(DS)에 역방항신호인 저전위 신호가 인가된 상태에서는 클럭신호단자(CK)에 클럭신호가 인가됨에 따라 상기에서 설명한 것과는 반대순서로 플립플롭(FF1), (FF2)이 출력신호가 변화하므로 스텝핑모우터코일(L1-F4)에는 L1, L2→ L2, L3→ L3, L4→ L4, L1→ L1, L2순서로 전류가 흐르게 되어 스텝핑모우터는 역방항으로 한 스텝씩 구동된다.When the low potential signal, which is the reverse direction signal, is applied to the direction signal terminal DS, the clock signal is applied to the clock signal terminal CK, so that flip-flops FF 1 and FF are performed in the reverse order as described above. 2 ) As this output signal changes, the stepping motor coils (L 1 to F 4 ) are L 1 , L 2 → L 2 , L 3 → L 3 , L 4 → L 4 , L 1 → L 1 , L 2 As the current flows in the furnace, the stepping motor is driven one step in the reverse direction.

그리고, 인에이블신호단자(EN)에 인에이블신호가 인가되지 않는 상태, 즉 저전위신호가 인가된 상태에서는 앤드게이트(AND1)의 출력신호가 저전위상태를 유지하여 플립플롭(FF1), (FF2)의 클럭단자(CK1), (CK2)에 클럭신호가 인가되지 않으므로 스텝핑모우터는 정지상태를 유지하게 된다.In addition, when the enable signal is not applied to the enable signal terminal EN, that is, when the low potential signal is applied, the output signal of the AND gate AND 1 maintains the low potential state to flip the flip-flop FF 1 . Since the clock signal is not applied to the clock terminals CK 1 and CK 2 of (FF 2 ), the stepping motor maintains the stop state.

이상에서와 같이 본 고안은 클럭신호의 발생주기에 동기되어 스텝핑모우터의 구동속도가 결정되므로 스텝핑모우터의 구동속도를 적정등속도로 맞출 수 있게 되고, 스텝핑모우터구동 입력신호를 클럭신호 및 방항지시신호에 의하여 하드웨어적으로 발생시키게 되므로 마이크로 프로세서의 점유시간이 감소되어 몇개의 구동원(예를 들어, 타이프 라이터와 프린터)을 동시 구동하는데 매우 용이하게 된다.As described above, since the driving speed of the stepping motor is determined in synchronism with the generation period of the clock signal, the driving speed of the stepping motor can be adjusted to an appropriate constant speed, and the stepping motor driving input signal is converted into a clock signal and Since it is generated in hardware by the command signal, the occupancy time of the microprocessor is reduced, making it very easy to simultaneously drive several driving sources (for example, a typewriter and a printer).

Claims (1)

(정정) 방항지시신호단자(DS)를 익스클루시브오아게이트(EXOR1-EXOR4)의 일측입력단자에 접속하여 그들의 출력단자를 플립플롭(FF1), (FF2)의 입력단자(J1), (K1), (J2), (K2)에 접속하고, 클럭신호단자(CK) 및 인에이블신호단자(EN)를 앤드게이트(AND1)의 입력단자에 접속하여 그의 출력단자를 플립플롭(FF1), (FF2)의 클럭단자(CK1), (CK2)에 접속하며, 이 플립플롭(FF1), (FF2)의 출력단자(Q1), (Q2),를 상기 익스클루시브오아게이트(EXOR3),(EXOR2), (EXOR4), (EXOR1)에 각각 접속함과 아울러 버퍼(B1-B4)를 통하여 스텝핑모우터구동회로(1)의 입력단자(I1-I4)에 각각 접속하여 구성함을 특징으로 하는 스텝핑모우터 등속구동시 입력신호발생회로.(Correction) Connect the command signal terminal (DS) to one input terminal of the exclusive oragate (EXOR 1- EXOR 4 ), and their output terminals are the flip-flops (FF 1 ) and (FF 2 ) input terminals (J). 1 ), (K 1 ), (J 2 ), and (K 2 ), and the clock signal terminal (CK) and the enable signal terminal (EN) are connected to the input terminal of the AND gate (AND 1 ), and their output. flip-flop terminal (FF 1), a clock terminal (CK 1), and connected to the (CK 2), a flip-flop output terminal (Q 1) of (FF 1), (FF 2 ) of (FF 2), ( Q 2 ), Is connected to the exclusive oragate (EXOR 3 ), (EXOR 2 ), (EXOR 4 ), and (EXOR 1 ), respectively, and the stepping motor driving circuit 1 is connected to the buffer B 1 through B 4 . And an input signal generation circuit for driving stepping motors at constant speed, characterized in that they are connected to the input terminals (I 1 -I 4 ) respectively.
KR2019840014365U 1984-12-29 1984-12-29 Arrangement for starting electric motor KR870002213Y1 (en)

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KR870002213Y1 true KR870002213Y1 (en) 1987-06-24

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