KR940003007B1 - Arrangement for controlling brushless dc motor - Google Patents

Abstract

The PWM pulse generator for controlling DC motor includes OR gates (OR11,OR71) for storing motor control data temporarily, a switch (195) for providing initial value to a counter, up-down counters (180,185,190) for counting time according to initial value and reference frequency signal, comparators (151-156, 161-166) for comparing output signals of the latches (131-136, 141-146) and the up-down counters (180,185,190), OR gates (OR12-OR62) operated by output signal of the comparators and the borrows signal of the up-down counter (190), latches (141-146) for controlling input voltage applied to a motor by output signal of a flip-flop, and OR gates (OR13-OR63) for generating PWM pulse by output signals of the latches.

Description

PWM pulse generator for brushless DC motor control

1a, b, c, d is a circuit diagram of the present invention for a PWM pulse generator.

* Explanation of symbols for main parts of the drawings

100: micro process

111,121,131,141,116,126,136,146: Latch circuit

151,161,156,166: Comparator 180,185,190: Up / Down Counter

195: switch unit 171,176: flip-flop

200: decoder circuit INT: inverter

OR ₁₁ -OR ₁₃ , OR ₆₁ -OR ₆₃ , OR ₇₁ : Oagate

The present invention can be used for the speed controller of a brushless DC motor widely used in all industrial fields. In particular, the digital circuit configuration is simple and the pulse frequency and impact ratio are precise and stable. The invention relates to a PWM (Puise Width Modulation) pulse generator for controlling a brushless DC motor.

Conventionally, the PWM pulse generator circuit, which is the key to realizing the complete digitalization of the brushless DC motor speed controller, is composed of an analog circuit.

That is, such an analog circuit configuration is configured to generate a PWM pulse by comparing a triangular wave pulse and a command voltage, but when configuring the circuit in this manner, an intermediate interface (D / A converter) and various analog ICs ( The circuit configuration is complicated and expensive because an integrated circuit is required, and the motor control is performed because the impact ratio and frequency of the PWM pulse change by the gain and offset of the analog IC. There was a drawback of poor performance.

SUMMARY OF THE INVENTION The present invention has been made to solve the above drawbacks, and can be used without intervention of an intermediate interface by a simple circuit configuration by digital logic, and is applied from a microprocessor and an output of a counter operated by a reference frequency. By comparing the control data to generate a precise PWM pulse having the desired frequency and impact ratio to control the three-phase brushless DC motor by the PWM pulse generated to improve the performance of the motor drive circuit, which is attached to the accompanying drawings Referring to the present invention in detail as follows.

1a, b, c, and d are circuit diagrams of the present invention for generating six PWM pulses to the OUT ₁ to OUT ₆ terminals. First, an OA gate (OR ₁₁ -OR ₇₁ ), a decoder circuit 200, and a latch circuit 111-116 (121) operating in accordance with a control signal applied from the micro process 100 to temporarily store data for motor control. (126) (131-136) (141-146), switch unit (195) for applying input data to the counter in accordance with the switch on and off to control the frequency of the pulse, and by the switch unit (195) Up / down counters 180, 185 and 190 that perform counting according to the reference frequency signal from the set data, the latch circuits 131-136, 141-146 and up / down counters 180, 185 Comparators (151-156) (161-166) for comparing the output of the 190, the comparison output signal of the comparators (151-156) (161-166) and the Borrow of the up / down counter (190) Oagate (OR ₁₂ -OR ₆₂ ) and flip-flops (171-176) operating in accordance with the signal, the latch rotation for controlling the output of the flip-flop (171-176) and the motor on, off The furnaces 141-146 and the oragates OR ₁₃ -OR ₆₃ which generate PWM pulses in accordance with the operation of the latch circuits 141-146.

The switch unit 195 is configured by connecting pull-up resistors R ₁ -R ₁₂ and DIP switches SW ₁ (SW ₂ ).

Referring to the effects of the present invention configured as described above in detail.

)중 한 개의 칩 실렉트신호(

)가 출력된다. 이 출력된 칩실렉트 신호가 제1b 및 c도 각각의 12개의 래치회로(111-116)(121-126)중 (b)도의 2개의 래치회로(111)(121)의 클럭단자(CK)에 입력되어 상기 래치회로(111)(121)가 동작하게 된다. 따라서 상기 마이크로 프로세스(100)의 데이타버스(D₀-D₇)(D₈-D₁₅)단자로부터 모터 제어를 위한 데이타들이 출력되어 8비트 래치회로(111)(121)의 입력단자(IN)로 각각 인가된다. 이때 상기 데이타버스(D₀-D₇)(D₈-D₁₁)를 통해서는 PWM 펄스의 충격비에 해당하는 데이타가 출력되며, 제1c도의 한쌍의 래치회로(116)(126)에서는 다른 데이타버스(D₁₂, D₁₃)를 통해 모터의 온, 오프 신호가 각각 출력된다.First, in the decoder circuit 200 of FIG. 1A, a signal of an address bus output from the microprocessor 100 is input and six chip select signals (

One chip select signal ()

) Is output. The output chip select signal is supplied to the clock terminals CK of the two latch circuits 111 and 121 shown in (b) of the twelve latch circuits 111-116 and 121-126 in the first and second circuits. The latch circuits 111 and 121 operate to be input. Accordingly, data for motor control is output from the data bus terminals D ₀ -D ₇ (D ₈ -D ₁₅ ) of the microprocessor 100 to input the input terminals IN of the 8-bit latch circuits 111 and 121. Are applied respectively. At this time, the data corresponding to the impact ratio of the PWM pulse is output through the data bus (D ₀ -D ₇ ) (D ₈ -D ₁₁ ), other data in the pair of latch circuits (116, 126) of Figure 1c. The on and off signals of the motor are output through the buses D ₁₂ and D ₁₃ , respectively.

)는 (b) 및 (c)도의 12개의 래치회로(111-116)(121-126)를 동시에 다른 12개의 래치회로(131-136)(141-146)로 인가시키기 위해 사용된다.The other chip select signal output from the OR gate OR _{71 of} FIG.

Are used to apply the twelve latch circuits 111-116 (121-126) in FIGS. (B) and (c) to the other twelve latch circuits 131-136 (141-146) at the same time.

)와 판독/기록신호(R/

)가 인가되고, 그의 오아게이트(OR₁₁-OR₆₁)의 타측(②) 입력단자에는 칩 실렉터신호(

)가 인가된다.In addition, a control signal for operating a logic circuit is applied to the orifices OR _{11 to} OR ₆₁ connected to the latch circuits 111 to 116 and 121 to 126, respectively. A strobe signal is provided at one input terminal (①) of the ora gates OR _{11 to} OR _{61 in} FIGS.

) And read / write signals (R /

) Is applied, and the chip selector signal () is input to the other (②) input terminal of the Oagate (OR ₁₁ -OR ₆₁ ).

) Is applied.

The oA gates OR ₁₁ -OR ₆₁ are used to drive the latch circuits 111-116 (121-126) of the next stage, and operate according to an input control signal to operate the latch circuits 111-116 ( Supply the clock pulse to the controller. The latch circuits 111-116 and 121-126 operate according to the clock pulse to temporarily store data, and then input terminals IN of the latch circuits 131-136 and 141-146 of the next stage. To print the data.

)로부터 클럭신호를 받아서 상기 데이타(D₀-D₇)(D₈-D₁₁) 를 다음단의 비교기(151-156)(161-166)의 입력단자(IN)로 출력한다. 한편, 상기 비교기(151-156)(161-166)의 다른 입력단자에는 제1d도에서의 서로 직렬 접속되어 있는 4비트 업/다운 카운터(180)(185)(190)의 출력데이타가 인가된다. 상기 업/다운 카운터(180)(185)(190)는 다운입력단자(DN)를 통해 인가되는 20MHZ의 기준 주파수신호에 따라 동작하여 스위치부(195)에 의해 설정된 입력 데이타에서부터 카운팅된 데이타를 출력한다.The latch circuits 131-136 and 141-146 in FIGS. 1b and c show data D ₀ -D ₇ (D _8- ) received from the latch circuits 111-116 and 121-126 of the preceding stage. the chip selector to D ₁₁₎ was temporary storage (

The clock signal is received from the data signal D ₀ -D ₇ and outputs the data D ₀ -D ₇ (D ₈ -D ₁₁ ) to the input terminal IN of the next comparators 151-156 and 161-166. On the other hand, the output data of the 4-bit up / down counters 180, 185 and 190 connected in series with each other in FIG. 1d is applied to the other input terminals of the comparators 151-156 and 161-166. . The up / down counters 180, 185, and 190 operate according to a reference frequency signal of 20 MHz applied through the down input terminal DN to output counted data from the input data set by the switch unit 195. do.

Here, the switch unit 195 is to adjust the frequency of the carry pulse (Carry pulse), the up / down depending on whether the DIP (Dual In-line Package) switch (SW ₁ ) (SW ₂ ) on or off The counting initial value of the counters 180, 185, 190 is changed. The switch (S ₁₎ turns on, the up / down a low signal to the input terminal (A) of the counter 180 is applied to the switch (S ₁₎ when off, and applied with the high signal, the up / down counter 180, The initial value is set in the other input terminal of (185), (190) as above.

Therefore, in the comparators 151-156 and 161-166 of FIG. 1C, the microprocessor of FIG. 1A is used to change the impact ratio of data and pulses output from the up / down counters 180, 185, and 190. The data set by 100 is compared and a comparison signal is output. When the counting data is the same as the setting data by the microprocessor 100, a low signal is output through the terminals A = B of the comparators 151-156 and 161-166, and the oragate OR _12. -OR _62), is at a low signal is outputted in the low output signal is applied to the clear terminal (CLR) of flip-flops (171-176). As a result, the flip-flops 171-176 in FIGS. 1b and c are reset, and a low signal is applied to one input terminal 1 of the ora gates OR _{13 to} OR ₆₃ .

Therefore, the data bus of the microprocessor 100 of FIG. 1A is connected to the other input terminal (2) of the OR gate (OR ₁₃ -OR ₆₃ ) connected to the output active terminal Act ₂ of the latch circuits 141 and 146. Since the on / off control data of the motor output through the (D ₁₂ ) (D ₁₃ ) terminal is in the normal operating state except when it is All time on or All time off, The PWM signals in the low state are output from OUT ₁ to OUT ₆ at the oragates OR _{13 to} OR ₆₃ .

Meanwhile, as described above, the up / down counters 180, 185, and 190 continue counting down, and a Borrow signal is transmitted through the right terminal Bo of the up / down counter 190. When generated, the clock pulse is applied to the clock terminal CK of the flip-flops 171-176 to operate the flip-flops 171-176. At this time, in the flip-flop 171-176, the low signal output from the terminal of the latch circuit 146 is inverted through the inverter INT during normal operation. Since the inverted high signal becomes active (Act ₁ ) and is input to the data terminal (D) of the flip-flops (171-176), the high signal is output through the output terminal (Q) of the flip-flop (171-176). do. The high signal thus output is applied to one side (①) input terminal of the oragate (OR ₁₃ -OR ₆₃ ) of FIGS. 1b and c so that the signal of the other (②) input terminal of the other (OR ₁₃ -OR ₆₃ ) is provided. Irrespective of this, high signal is output and high signal is output to OUT ₁ -OUT ₆ terminal. Thus, the 3-phase brushless DC motor can be controlled by the output high signal, that is, PWM pulse.

According to the present invention operated as described above, when the brushless DC motor driving circuit is configured as a digital logic circuit, a D / A converter is not required, so the circuit configuration is simplified, and the frequency and impact ratio of the PWM pulse are also reduced. Since the motor can be controlled more accurately and stably than the conventional method, there is an effect that can provide a motor driving circuit with excellent performance.

Claims (1)

In the PWM pulse generator of the brushless DC motor driving circuit, an OA gate (OR ₁₁ ) (OR ₇₁ ) for operating temporarily according to a control signal applied from the micro process 100 to temporarily store data for motor control, and a decoder circuit. (200) and latch circuits (111-116) (121-126) (131-136) (141-146), and a switch section for inputting a counting initial value to the counter according to the switch on and off for frequency control of the pulse. (195), up / down counters 180, 185, 190 for counting according to a reference frequency signal from data set by the switch unit, the latch circuits 131-136, 141-146, and Comparators (151-156) (161-166) for comparing the outputs of the up / down counters (180, 185, 190), and according to the comparison output signal of the comparator and the right signal of the up / down counter (190). Oagate (OR ₁₂ -OR ₆₂ ) and flip-flop (171-176) in operation, the output of the flip-flop (171-176) and the motor To control the on and off of the latch circuit 141-146 for controlling on and off and the oragate (OR ₁₃ -OR ₆₃ ) generating a PWM pulse according to the operation of the latch circuit 141-146 and the motor. PWM pulse generator for brushless DC motor control characterized in that it comprises an inverter (INT) for.

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