SU612412A1 - Logical probe - Google Patents

Description

(54) LOGICAL PROBE

The invention relates to a pulse technique and can be used to indicate the states of potential and pulse logic elements.

Devices for indicating the states of logic elements are known, which contain a unit for determining and indicating a logical state of the element being tested and a generator of tacts of OUT pulses 1.

In such devices, for the indication of single and rarely repeated pulses, the device must be periodically set by the operator to its original state, which leads to the loss of information about the pulse period. The absence of an emitter repeater at the device input leads to an increase in the current consumed from the logic element being tested, and the presence of elements for indicating idle levels increases the current consumed by the device in the idle state when there is no signal at the input.

Closest to the proposed invention is a logical probe containing a block for determining and indicating logical states, the first and second inputs of which are connected to the input of the device through a prohibition element and an emitter follower, generator 2.

This logic probe has a high input impedance and allows, besides the operating levels of the logic signal, to indicate the absence of a connection (idle) at the 5th input, as well as intermediate levels of the logic signal of the off state of the indicator elements, thus reducing the current consumed by the device. generally. However, this logical probe does not possess

The necessary accuracy of indication of low-frequency, foreign and rarely repetitive pulses of short duration, as well as high-frequency pulsed signals with a large duty cycle.

The purpose of the invention is to increase the accuracy of the display.

5 This is achieved by the fact that a logical probe, containing a block for determining and indicating loginstation states, the first and second inputs of which are connected to the device input through a prohibition element and an emitter follower generator, is entered with an RS flip-flop with two elements AND at the inputs, an element NOT and a delay element based on a D-flip-flop, the synchronization information input of which is connected to the generator output, the forward and inverse outputs of the delay element are connected to

5 by the third and fourth inputs of the unit for determining the logical state and with the first inputs of the elements AND the RS flip-flop respectively, the second inputs of which, the nerve is not very direct and the second through the element NOT, and connected to the output of the emitter follower.

The drawing is a block diagram of the proposed logical probe.

The logical probe contains the emitter iovtoritel 1, the element is closed 2, the generator 3, the element 4, two elements 5 and 6, RS trigger 7, the delay element based on the D-trngger 8, block 9 of determination and indication of logical states.

Logical probe works as follows.

In the absence of an input signal or in the presence of a logical unit at the probe input, a high potential is formed at the output of the 1st emitter innovator 1. In this case, the RS flip-flop 7 is set to the zero state, and the D-flip-flop 8 is set to one. The feedbacks from the outputs of the D-flip-flop 8 to the inputs of the And 5 and 6 elements are made so that only the signal whose logic level is opposite to the previous one is allowed to pass through the RS-flip-flop 7.

Thus, if the input unit has a logical unit at the input, the device is set to the state when at the first input of element 5 there is a low potential from the output of the D-flip-flop 8. and at the first input of the element i 6 it is high. Since the second input of the E and And 5 is a high input notification, and the second input of the And 6 element, but connected to the output of the repeater 1 through the HE 4 element, is low, then the outputs e; 1ements And 5 and 6 have a low potential, that is, there are no setting signals at the inputs of the RS-trngger 7. When changing the input logic level from one to zero, at the second input of the logic element And 6 connected to the output of the emitter novtoritel 1 through the element NOT 4, a high notice will appear and the output of the RS-trngger 7 will pass to the output element 6 condition.

Since the first inputs of the elements And 5 n

6 are connected to the output of the RS-flip-flop 7 via the delay element based on the D-flip-flop 8, the synchronization information input of which is connected to the output of the generator 3, then enabling the setting of the RS-flip-flop

7, in the opposite state, will arrive at the first inputs of the And 5 and 6 elements with a delay equal to the follow-up period of the generator pulses.

Thus, when a high-frequency pulsed high-frequency pulse is supplied at the input with any duty cycle (the period of the input pulses is less than the clock generator period), the output of the D-flip-flop 8 will generate pulses whose duration is equal to the period of the tact generator, and the next-period Since the clock oscillator is not of the same nature, and the pulse duration is less, then pulses with a duration will be generated at the output of the D-trnger 8.

equal to the period of the clock generator and frequency, equal to the frequency of the input signal.

The prohibition element 2 generates a low level at the output when the input signal is absent or goes beyond the tolerance of logic levels. The low level of the sngnal, the input on the input of the block 9 for determining and indicating logical states, prohibits the inclusion of display elements that indicate the state of the zero and single outputs of the D-flip-flop 8.

Consequently, when there is a logic zero or one at the probe input, the corresponding display element is lit. In the presence of a high-frequency pulse signal, both are m

display element, in the presence of a low-frequency pulse signal, the display elements are switched with the frequency of the signal. In the absence of or beyond the limits of the donka of the logical levels of the input signal, both elements are absorbed.

Taking into account the fact that when simultaneously supplying to R n S the inputs of the D-flip-flop

8 low logic level, at its single and zero outputs a high level is simultaneously present, it is possible to exclude a block

9 determine and display logical states by connecting display elements directly to the outputs of the D-trngger and implement the connection shown in the figure.

Unlike well-known circuits, the proposed logic probe circuit makes it possible to accurately indicate the presence of not only potential, but also pulse logic signals, as well as determine the polarity, duration and frequency of single and rarely repeated pulse signals, which makes it indispensable for debugging logic circuits.

The proposed scheme contains a significantly smaller amount of equipment compared to lime devices of similar purpose.

Claims (2)

1. "Instruments and control systems, 19/4,. About 12, p. 38-39. 2. "Instruments and systems, 1 control, 1974, Up to 4, p. .