SU1108373A1 - Probe for checking logic devices in emitter-coupled integrated circuits - Google Patents

Abstract

A PROBE FOR CHECKING LOGICAL DEVICES ON MICROCHARGES OF EMITTER-ASSOCIATED LOGIC, containing four comparators, the first inputs of which are connected to the corresponding outputs of the source of the reference voltage, the second inputs of the first and fourth comparators - with the input of the probe through the protection unit and the chantry key codes and the chantry key codes, and the chantry keyboards and the chantry keyboards. In order to enhance functionality due to the detection and recording of nanosecond pulsed signals, a peak detector detector, two single-oscillators, four ment 2 AND-NOT, element 2, RS trigger and switch, the first peak detector is connected between the output of the protection unit and the second input of the second comparator, the second peak detector is connected between the output of the protection unit and the second input of the third comparator, the outputs of the first and second the comparators are combined according to the installation OR scheme and connected to the first input of the first element 2И-NOT and to the first input of the second element 2И-НЕ, the outputs of the third and fourth comparators are combined according to the installation scheme OR, and connected to the first input of the third floor 2I-NOT and to the second input of the second element 2I-NOT, the output of the first element 2I-NOT is connected to the input of the first one-vibrator and to the first input of the fourth element 2I-NO, the output of the third element 2I-NOT is connected to the input of the second one-vibrator and to the first input element 2I, the output of the first one-shot is connected to the second input of the third element 2I-NOT and to the second input of the fourth element 2I-NO, the output of the second one-shot is connected to the second input of the first element 2I-NO and to the second input of the element 2I, the output of the fourth O C element 2I -Not connect It is connected to the first input of the first display element, the output of element 2I is connected to the second input of the first indication element, the output of the second element 2I-NOT oo is connected to the S-input of the RS-Gyra, the R-input of the RS-flip-flop is connected to the first contact of the switch, A second switch contact is connected to. the common bus, the input of the source of reference voltages is connected to the power bus, the output of the RS flip-flop is connected to the input of the second display element.

Description

The invention relates to electrical measuring technology and can be used to test devices built on logic elements of emitter-coupled logic (ECL). A logic tester is known for testing devices on ECL logic elements, displaying logic levels on the outputs of the microcircuits being tested. The tester contains six comparators, the outputs of which are connected to the inputs of two OR circuits and the inputs of the circuit AND respectively, the source of reference voltages, three amplifiers connected in series and three indicator elements, the corresponding inputs of the comparators are connected to the SON unit; the probe is the closest to the invention. containing four comparators, one inputs of which are connected to the corresponding sources of the reference voltage, and other inputs to the input of the probe through a protection circuit and three indicator voltages of the element controlled by the appropriate commarators 2. The disadvantage of these probes lies in the limited functional possibilities ... probes induce only static or slowly varying (pulse duration not less than 100 ms) signals, while the tested microcircuits We work with nanosecond signals, ECL. The aim of the invention is to enhance the functionality of the probe by detecting and registering pulse signals of nanosecond duration. The goal is achieved in that a probe containing four comparators, the first inputs of which are connected to the corresponding outputs of the source of reference voltages, the second inputs of the first and fourth comparators to the input of the probe through the protection unit and two indicators, includes two peak detectors, two single vibrators, four elements 2I-NOT, element 2I, RS-trigger and switch, with this the first peak detector is connected between the BF.ixonoM protection unit and the second input of the second comparator, the second peak detector is connected between the output of the 3au iiT-t, i and the second input the house of the third comparator; the first and second KONmapaTopOB are combined according to the installation OR scheme and connected to the first input of the first element 2I-NOT and to the first input of the second element 2I-NO, the outputs of the third and fourth comparators are combined according to the installation scheme OR and connected to the first input of the third element 2I-NOT and to the second input of the second element 2И-NOT, the output of the first element 2И-NOT is connected to the input of the first one-shot and to the first input of the fourth element 2-NO, the output of the third element 2-AND is NOT connected to the input of the second one-shot and to the first input of the element 2И, the output The first one-shot is connected to the second input of the third element 2I-NOT and to the second input of the fourth element 2I-NO, the output of the second one-shot is connected to the second input of the first element 2I-NOT and to the second input of the element 2I, the output of the fourth element 2I-NOT is connected to the first input the first element of the display, the output of element 2I is connected to the second input of the first element of the display, the output of the second element 2I is NOT connected to the S-input of the RS flip-flop, the R-input of the RS-flip-flop is connected to the first end .. i ..- ij CCU .. tact switch, the second contact switch on The key to a common bus, the input reference voltage source coupled to the power bus, RS-flip-flop output being connected to the input of the second display element, Fig. 1 shows the block diagram of the proposed probe; Fig, 2 - modes of operation of the probe. The probe contains the input 1, block 2 protection, peak detectors 3, 4, comparators 5-8, elements 9, 10, 11 2I-NOT, the detector 12, element 13 2I-NO, one-shot 14, element 15 2I, display element 16, RS trigger 17, switch 18, display element 19, reference voltage source 20, power bus 21, common bus 22. When implementing this device, it should be noted that peak detectors 3, 4 are made according to the basic amplitude detector circuit and have discharge circuits - input circuits of comparators 6, 7. The second inputs of the first 5 and fourth B comparators are connected to the output of the protection unit 2, the second inputs of the second 6 and 7 of the third comparators are connected to the output of the blsp-sa 2 protection through the corresponding peak detectors 3 and A, the outputs of the first 5 and second 6 comparators are combined according to the wiring OR circuit and connected to the first input of the first element 9 2I-NOT and to the first input do the second element 10 2I-NOT, the outputs of a third of its 7 and fourth 8 comparators are combined according to the installation scheme OR and connected to the first input of the third element 11 2I-NOT and to the second input of the second element 10 2I-NO, the output of the first element 9 2I-NO connected to the input of the first one-shot 12 and to the first input of the fourth element 13 2I-NOT, the output of the third element 11 2I-NO is connected to the input of the second one-shot 14 and to the first input of the element 15 2I, the output of the first one-shot 12 connected to the second input of the third element 11 2I-NOT and to the second input of the fourth element 13 2I-NOT, the output of the second single-vibration 14 is connected to the second input of the first element 9 2I-NO and to the second input of the element 15 2I, the output of the fourth element 13 2I-NO is connected to the first input of the first display element 16, the output of the element 15 2I connected to the second the input of the first display element 16, the output of the second element 10 2I-NOT is connected to the S-input of the RS-flip-flop 17, the R-input of the RS-flip-flop is connected to the first contact of the switch 18, the second contact of the switch 18 is connected to the common bus 22, the input the source of the 20 voltages is connected to the power bus 21, the output of the RS flip-flop 17 is connected to the input of the second display element 19 The probe operates as follows. After supplying the supply voltage to the busbars 22 and 21, the source of the reference voltage 20 generates voltages and, ", and, and. . The magnitudes of the reference voltages are chosen so that the comparators 5 and 6 determine the zone of permissible values of logic and the comparators 7 and 8 are the zone of permissible values of logic 1. Suppose, in the initial state, input 1 is connected to a controlled point, the voltage in which is greater than the logical level. but less than the logical level 1, i.e. at the input of the probe intermediate logic level. At the same time, at the outputs of comparators 5-8, logic level 0, at the outputs of elements 9, 11 2И-NOT levels of logical 1, at outputs of one-shot 12 and 14 levels of logical 1, at output of element 13 2И-NOT logical level O, at output of element 15 2И the logic level 1, the display element 16 lights up fully, indicating the intermediate level at input 1. When input 1 is connected to a controlled point having a potential of logic 1, the outputs of comparators 5, 6 will be logic level 1, at outputs of comparators 7, 8 logic O one-way outputs ditch 12, 1A levels logical 1, at the output of element 9 2I-NOT logical level O, at the output of elements 11, 13 2I-NOT logical level 1, at the output of element 15 2I logical level 1. Display element 16 shines brightly, since its inputs are logical 1 levels, indication. logical logical 1 at input 1. When input 1 is connected to a controlled point, which has a potential of logical O, the outputs of comparators 5, 6 will have a fool plate of logical O at the outputs of comparators 7, 8 level of logical 1, at the outputs one-shot 12, 14 levels logical 1, the output element 9 2I-NOT level of logic 1, at the output of elements 11, 13 2I-NOT level of logical O, at the output of element 15 2I level of logical O. Element 16 of the display does not light, indicating the level of logical O at input 1. Time interval required for visual indication A single pulse of nanosecond duration is 200 ms. During this time interval, the probe does not indicate the arrival of new pulses (see figure 2). The 200 ms time interval is obtained from time intervals of 100 ms duration, overlaid by single vibrators 12 and 14. For example, when a nanosecond positive pulse arrives, the peak detector 3 grows no pulse to a value sufficient to trigger the comparator 6. On the comparator 6, the pulse has a positive pulse , it is inverted by the element 9 2I-NOT and starts the one-shot 12 with a negative front. The one-shot 12 produces a negative signal with a duration of 100 ms. This signal enters the input of element 11 2I-NOT and blocks the passage of signals from the output of comparator 7. At the outputs of elements 13 2I-NO and 15 2I, logic level 1 will be 1 for 100 ms, and display element 16 will turn on for 100 ms and will flash about a positive impulse at the probe input. The negative edge, inverted by the element 11 2I-NOT signal with a duration of 100 ms, triggers the one-shot 14. It produces a negative signal with a duration of 100 ms, which enters the input of the element 9 2I-NOT and blocks the passage of signals from the comparator 6 through it. A single nanosecond pulse takes 200 ms.

With a high frequency of input pulses, when the time interval between pulses is less than the time of peak detectors to the threshold levels of comparator 6 and 7, the peak detectors will not have time to discharge and the outputs of comparators 6 and 7 will be logical 1, which will result in single vibrators 12 and 14 in the self-oscillation mode with a pulse repetition period of 200 ms.

The indication element 16 with a flashing frequency of 5 Hz will indicate the passage of a high-frequency sequence of pulses.

The registration of a single pulse is carried out as follows. By pressing the switch 18, the RS flip-flop 17 is transferred to a state in which the output Q is a logic level O. The display element 19 does not light up. When a positive or negative pulse arrives at input 1, a short-term combination of two logical 1 occurs at the outputs of the comparators 5, 6 and 7, 8 and at the inputs of the 10 2I-NOT element, the output of the 10 2I-NO element and the RS flip-flop at the S input 17 Wits negative pulse switching RS flip-flop 17. The Q output of the RS flip-flop 17 establishes the logic level 1. The display element 19 lights up, indicating the appearance of a negative or positive pulse at input 1

The use of the proposed probe, which has wider functional capabilities for detecting and recording pulsed signals of nanosecond duration, makes it possible to increase the plausibility, reliability, and speed of the control of logic devices built on ECL chips.

1- indicator will not stop

1- indicator shines in full

J- indicator will clear

t HC

Figg

Claims (2)

Sampler for checking logic devices on microcircuits of emitter-coupled logic, containing four comparators, the first inputs of which are connected to the corresponding outputs of the reference voltage source, the second inputs of the first and fourth comparators - with the probe input through the protection unit and two indicators, characterized in that In order to expand functionality by detecting and recording pulsed signals of nanosecond duration, two peak detectors, two one-shots, four elements are introduced into it 2 NAND, element 2 AND, RS-trigger and switch, while the first peak detector is connected between the output of the protection unit and the second input of the second comparator, the second peak detector is connected between the output of the protection unit and the second input of the third comparator, the outputs of the first and second comparators combined according to the assembly scheme OR and connected to the first input of the first element 2I-NOT and to the first input of the second element 2I-NOT, the outputs of the third and fourth comparators are combined according to the circuit OR, and connected to the first input of the third element 2I-NOT and to the second input of the second element 2I -NOT, the output of the first element 2I-NOT connected to the input of the first one-shot and to the first input of the fourth element 2I-NOT, the output of the third element 2I-NOT connected to the input of the second one-shot and to the first input of 2I, the output of the first one-shot connected to the second input of the third uh element 2I-NOT and to the second input of the fourth element 2I-NOT, the output of the second one-shot connected to the second input of the first element 2I-NOT and to the second input of the element 2I, the output of the fourth element 2I-NOT connected to the first input of the first indication element, the output of 2I connected to the second input of the first indication element, the output of the second element 2 is NOT connected to the S-input of the RS-trigger, the R-input of the RS-trigger is connected to the first contact of the switch, the second contact of the switch is connected to. common bus, the input of the reference voltage source is connected to the power bus, the output of the RS-trigger is connected to the input of the second indication element. SU „„ 1108373