JPH04180437A - Gate signal generating circuit - Google Patents

Abstract

PURPOSE:To attain the use of a digital reception signal discrimination circuit by using a signal delay circuit to delay a detection output of a signal detection circuit by a prescribed time, using the signal for a clock for latching the reception signal and allowing a latch circuit to latch the signal. CONSTITUTION:When a signal detection circuit 4 detects the presence of a data between differential input terminals, an output signal Y goes to an H level and a signal Y is inputted to a shift register 5. A clock signal from a clock terminal 1 is subject to 1/2 frequency division by a frequency divider 6 and the resulting signal is given to the shift register 5 as a shift clock, then a register 5 delays the signal Y and gives it to a data input D of an FF 7. In order to latch the data given to the FF 7, a differential receiver 8 gives a reception signal converted into a TTL level to a clock input for latch of the FF 7. Thus, a gate signal used for extracting the data signal is generated at a Q output of the FF 7. Through the circuit constitution above, the gate signal generating circuit is formed by using a shift register and an FF.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention provides a gate signal used to separate a link test pulse signal for confirming that a transmission medium is connected from a normal data signal. This relates to a gate signal generation circuit that generates, for example, IEEE802.
3 standard l0BASE-T media connection equipment (MAU
”) is used in the received signal discrimination circuit.

[Conventional technology] Conventionally, IEEE802.3 standard (C8MA/CD method)
A LAN called 10BASE-T, which has a transmission speed of IOM bits/second and uses twisted pair wires as a transmission medium, is in widespread use. Since the transmission medium of 10BASE-T is composed of twisted pair wires like telephone lines, it is possible to build a LAN horizontally using already wired telephone lines, which often requires changing the floor layout. Suitable for office use.

10BAS uses such twisted pair wire as the transmission medium
There is a high possibility that ET will become unable to communicate due to a disconnection in the transmission medium. Therefore, a link test pulse signal is inserted before and after the normal data signal to confirm that the transmission medium is connected. ing. Therefore, the media connection device M AU (Media
Access Unit) requires a received signal separation circuit that extracts only necessary data signals from the received signals.

[Problems to be Solved by the Invention] A conventional received signal separation circuit is constructed using a clip-flop, an AND circuit, and a monostable multivibrator. However, when using a monostable multivibrator, it is necessary to externally attach a resistor and capacitor for setting the time constant, so there is a problem that recent programming devices cannot be used. In addition, the received signal is detected by a differential receiver, but depending on the sensitivity of this differential receiver, there is a problem that the link test pulse signal may be detected as one pulse or as two pulses. .

The present invention has been made in view of the above points, and its purpose is to convert a gate signal generation circuit that generates a gate signal for separating a normal data signal and a link test pulse signal into a digital circuit. The purpose is to prevent confusion between link test pulse signals and normal data signals.

[Means for Solving the Problems] In order to solve the above problems, the gate signal generation circuit of the present invention uses a link test pulse signal and a normal link test pulse signal for confirming that the transmission medium is connected. In an information transmission device in which data signals and data signals coexist on the same transmission medium in a time-division manner, as shown in FIG. A signal delay circuit such as a shift register 5 that delays the detection output of the signal for a predetermined period of time, and a flip-flop 7 that uses the output of the signal delay circuit as a latched input and uses the received signal from the transmission medium as a clock input for latching. A latch circuit is provided, and the latch output of the latch circuit is used as a gate signal for detecting a data signal.

[Operation] According to the present invention, the detection output of the signal detection circuit 4 that detects the presence of a received signal from the transmission medium is delayed for a predetermined period of time, and the delayed signal detection output is detected from the transmission medium. The received signal was latched as a clock input for latching, and the latch output was used as a gate signal for data signal detection. Therefore, a signal delay circuit such as the shift register 5 and a latch circuit such as the flip-flop 7 are required. It is possible to configure a gate signal generation circuit by using this, and it becomes possible to convert the received signal discrimination circuit into a digital circuit.

Furthermore, by appropriately setting the delay time of a signal delay circuit such as the shift register 5, it becomes possible to reliably distinguish between a normal data signal and a link test pulse signal.

[Embodiment] FIG. 1 is a circuit diagram of an embodiment of the present invention. CSMA/
The transmission line code in a CD-based LAN is a Manchester code, and if the data transmission rate is 10 Mbits/sec, the baud rate is 20 M samples/sec. Therefore,
A 20 MHz clock signal is input to clock terminal 1. The signals between the differential input terminals 2 and 3 are differentially amplified by the differential receiver 8 and input to the signal detection circuit 4.

The signal detection circuit 4 sets the output signal Y to a "High" level when a received signal is present, and uses this as a data input to the shift register 5. The clock signal at the tarlock terminal 1 is divided by a frequency of 1/2 (10 MHz) by a frequency divider 6, and becomes a shift clock for the shift register 5. The fourth bit output Q of the shift register 5 becomes the data output of the flip-flop 7. The output of the differential receiver 8 is input to the latch tarlock of the flip-flop 7. Note that when the output Q of the fourth bit of the shift register 5 and the output of the differential receiver 8 both become "'Low" level, the reset terminal R of the flip-flop 7 becomes "High" by the output of the AND gate 9 with negative logic input. ” level, and the flip-flop 7 is reset. The shift register 5 operates as a signal delay circuit, and the flip-flop 7 operates as a latch circuit, and the latch output Q of the slip-flop 7 is outputted from the output terminal 10 as a gate signal for data signal detection.

The operation of this embodiment will be explained below.

FIG. 2 is an operating waveform diagram when a normal data signal is received, and shows a 20 MHz clock signal input to clock terminal 1, differential receiver 8, signal detection circuit 4, frequency divider 6, and shift register. 5, the output waveforms of the flip-flop 7 and the gate 9 are shown. When the signal detection circuit 4 detects the presence of a data signal between the differential input terminals 2 and 3, its output signal Y becomes a "High" level, and this output signal Y is input to the shift register 5. Since the 20 MHz clock signal applied from the clock terminal 1 is divided by 2 by the frequency divider 6 and is applied to the shift register 5 as a 10 MHz shift clock, the shift register delays the signal Y by 420 times. The data of flip-flop 7 is manually operated.

In order to latch the data in the flip-flop 7, a received signal converted to a TTL level by the differential receiver 8 is supplied to the latch clock input of the flip-flop 7. If the received signal is a normal data signal, the fourth bit output Q of the shift register 5 is latched, and the output Q of the flip-flop 7 is outputted at a high level.

Further, when the output Q of the shift register 5 and the received signal of the differential receiver 8 both become "Low" level, the flip-flop 7 is reset by the output of the AND gate 9. Thereby, a gate signal for extracting a data signal can be generated at the output Q of the flip-flop 7.

FIG. 3 is an operational waveform diagram when a link test pulse signal for confirming that the transmission medium is connected is received. In this case, a one-pulse or two-pulse signal is obtained at the output of the differential receiver 8. The signal detection pressure rgJ path 4 detects this pulse signal and sets the output signal Y to “High”.
The shift register 5 delays this output signal Y by 4 bits and supplies it to the data output of the flip-flop 7. The flip-flop 7 outputs the output pulse of the differential receiver 8 to the latch signal. The 4th bit output Q of the shift register 5 is latched as a clock.However, in the link test pulse signal, the number of pulses is 1 or 2 pulses, which is less than a normal data signal, so the flip-flop The output Q of 7 is '
The link test pulse signal is never confused with a normal data signal.

[Effects of the Invention] In the gate signal generation circuit of the present invention, a link test pulse signal for confirming that the transmission medium is connected and a normal data signal are mixed in a time-sharing manner on the same transmission medium. In an information transmission device, the detection output of a signal detection circuit that detects the presence of a received signal from a transmission medium is delayed by a predetermined time using a signal delay circuit, and the received signal from the transmission medium is latched as a clock input for latching. Since the gate signal for detecting the normal data signal is generated by latching it in the circuit, it can be configured using shift registers and flip-flops, making it possible to convert the received signal discrimination circuit into a digital circuit. Furthermore, by appropriately setting the delay time in the signal delay circuit, it is possible to reliably distinguish between a link test pulse signal and a normal data signal.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is an operational waveform diagram when a normal data signal is received, and Figure 3 is an operational waveform diagram when a link test pulse signal is received. be. 1 is a clock terminal, 2.3 is a differential input terminal, 4 is a signal detection circuit, 5 is a shift register, 6 is a frequency divider, 7 is a flip-flop, 8 is a differential receiver, 9 is a gate circuit, 10
is the output terminal.

Claims (1)

[Claims] (1) In an information transmission device in which a link test pulse signal for confirming that the transmission medium is connected and a normal data signal coexist on the same transmission medium in a time-sharing manner, the received signal from the transmission medium a signal detection circuit that detects the presence of a signal, a signal delay circuit that delays the detection output of the signal detection circuit for a predetermined time, the output of the signal delay circuit as a latched input, and the received signal from the transmission medium as a clock input for latching. 1. A gate signal generation circuit comprising a latch circuit for detecting a data signal, the latch output of the latch circuit being used as a gate signal for detecting a data signal.