JPH0888655A - Data discrimination circuit - Google Patents

Abstract

PURPOSE: To allow the circuit to accurately discriminate the logic value of data representing '0' or '1' depending on the difference of duty ratios even when the falling of a signal is subjected to delay. CONSTITUTION: A delay circuit 11a delays data by one bit, discrimination circuits 11c to 11f use n-th bit data delayed by a signal output circuit (e.g. an exclusive OR circuit) 11b and (n+1)-th bit data not delayed, provide the output of a signal whose duty ratio is zero when the n-th bit data and the (n+1)-th bit data are identical to each other and provide the output of a signal whose duty ratio is not zero when the n-th bit data and the (n+1)-th bit data are different from each other so as to discriminate whether or not the logic value of a current bit is the same as a logic value of a right preceding bit thereby discriminating '0' or '1' of each of bit data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a data identification circuit,
In particular, the present invention relates to a data identification circuit for identifying the logical value of each bit data in a bit serial data string in which "0" and "1" are represented by the difference in duty ratio.

[0002]

2. Description of the Related Art There is a system in which a plurality of units are connected to a bus line, data is transferred between the units via the bus line, and a predetermined operation is performed. FIG. 6 shows an example of an on-vehicle audio / visual system in which various audio / visual devices are connected by a bus line. 11, 1 in the figure
2 is a commander (operation unit) which is a user interface, 21 is a system management unit (SCU), 31 is a head unit (HU), for example, an AM / FM tuner, a cassette tape player, a CD as an audio source.
Have a player. 32 is a cassette player, 33
Is a CD player, 34 is a DAT player, 35 is a digital audio source such as a mini disk player or a DCC (digital compact cassette) player, and 36 is A.
The M / FM tuner 37 is an audio processor. The reason that there is an audio source that overlaps with the audio source that constitutes the head unit (HU) 31 is that there is a case where it is desired to incorporate a higher-performance audio source than the audio source of the head unit into the system separately and enjoy it. Further, depending on the system, the audio source may be only the head unit or may not have the head unit, so that an arbitrary configuration can be adopted.

41 is a TV tuner
R) and 43 are navigation units. The video source can have an arbitrary configuration like the audio source, and there are a system without a video source, a system with only a TV tuner, a system including all video sources, and the like. Reference numerals 61 and 62 are amplifiers for amplifying audio signals, 63 is a visual monitor, for example, a liquid crystal display, and 64 is a remote controller. 71 (1 in the center of the line
Books with diagonal lines are cables having bus lines (communication lines) and analog audio signal lines (L, R), and connectors 72 are connected to both ends. 73 (2 in the center of the line
A cable having a slanted line) is a cable used for connecting a video composite display signal of a video unit, and has lines such as a video composite signal line and a remote control signal line, and connectors 74 are connected to both ends. 76
Is an audio cable for transmitting an analog audio signal, 77 is an optical fiber for transmitting digital data, has optical connectors at both ends, and an optical transmitter (E / O converter) is connected to the transmitting side optical connector. An optical receiver (O / E converter) is connected to the receiving side optical connector.

The communication line (bus line) 71 'included in the cable 71 is, as shown in FIG. 7 (a), each unit UNT.
It is internally connected to the through and is also connected to the controller CNT of each unit. The controller CNT takes in data sent from another unit via the communication line and performs a predetermined control, and can send the data to the other unit by putting the data on the communication line. With this configuration, all the units connected by the communication line 71 'can communicate with each other. The data is transferred bidirectionally on the communication line. The analog audio signal line 71 ″ is connected inside the unit UNT as shown in FIG. 7B, and the selector SEL follows the instruction from the controller CNT and the analog audio signal A1 and the audio source ADS sent from the preceding unit. One of the audio signals A2 output from is selected and transferred to the unit at the next stage.
Through connection is made inside the unit that does not have an audio source. Therefore, the analog audio signal output from the predetermined audio source reaches the audio processor (AP) 37 through the analog signal line 71 ″, where it is subjected to audio signal processing and output to the amplifier.

Similar to the analog audio signal line, a predetermined image signal is selected in each part of the video signal line, passes through each video unit, reaches the visual monitor 63, and is displayed on the display screen. The optical fiber is connected to the audio processor 37 via another digital audio source or directly. The audio processor 37 selects predetermined digital audio data, DA-converts it, and outputs it to the amplifiers 61 and 62. The remote control signal output from the remote control 64 is the commander 11 and the visual monitor 63.
It is received by the remote control light receiving unit provided inside. Upon reception of the remote control signal, the commander 11 sends out a predetermined command to the communication line based on the instruction from the remote control as in the case of the instruction by the key operation. Visual monitor 63
When the remote control signal is received, the remote control signal is sent to each video unit via the cable 73. Since the remote controller 64 can instruct the individual operation of each video unit, each video unit takes in the remote control signal and executes the instructed operation.

FIG. 8 is a block diagram of a bus driver provided between the controller CNT of each unit and the bus line 71 '. BUOC is a bus output circuit, BUIC is a bus input circuit, and bus line 71' is a differential two-wire line. It is a formula, + Bus, -Bu
It has 2 lines of s. The high level of + Bus is 3V and low level 1V, and the high level of -Bus is 4V and low level 2V. When outputting data, controller CN
When a high level signal is output from T, the signal is inverted by the inversion unit INV and becomes a low level. Therefore, PN
Both the P transistor TR1 and the NPN transistor TR2 are turned on. As a result, the + Bua line has a high level of 3V.
(= R6 / {R6 + (R5 // R1)}) is output, and low level 2V (= (R2 // R4) / {R3 + (R2 // R4)}) is output to the -Bus line. . /
/ Means a parallel combined resistance. On the other hand, controller C
When a low level signal is output from NT, the signal is inverted by the inversion unit INV and becomes a low level. Therefore, P
Both the NP transistor TR1 and the NPN transistor TR2 are turned off. As a result, the + Bua line has a low level of 1V.
(= R6 / (R5 + R6)) is output, and high level 4V (= R3 / (R3 + R4)) is output to the -Bus line.

When reading data from the bus line,
Comparator C for signal voltage V +, V- on + Bus line and -Bus line
Compare with MP, and if V +> V-, high level (= 5
V) and V + <V-, a low level (= 0V) is output. The data transferred via the bus line in the above system has the format shown in FIG.
(Start of message) is provided, followed by 80-bit data, EOD (End of data), 8-bit response, and finally EOM (End of message).
As shown in FIG. 10, the width of 1 bit is 24 μs, and “0” is represented by a waveform in which the first 16 μs is H (high level) and the subsequent 8 μs is L (low level),
Further, "1" is expressed by a waveform of H level for the first 8 μs and L level for the subsequent 16 μs. The SOM has a 2-bit width (48 μs), 32 μs in the first half has an H level waveform, and 16 μs in the latter half has an L level waveform. As described above, the high level period (duty ratio) is different between "0" and "1". Therefore, the controller CNT (FIG. 8) is set to the high level period of both as shown in FIG. 11 (a). The data is identified at the center of the difference. That is, the controller CNT is the bus input circuit BUIC.
At the timing of 12 μs after the output signal of FIG. 8 rises from the L level to the H level, H and L of the output signal are output.
Check "0" for H level and "0" for L level
The data is read as 1 ".

[0008]

By the way, in the conventional data reading method, the fall from the H level to the L level is caused by the deterioration, variation, and other reasons of the element in FIG.
When the delay is 4 μs or more as shown by the hatched line in (b), there is a problem that the “0” and “1” cannot be distinguished.
From the above, an object of the present invention is to provide a data discriminating circuit which can discriminate correctly between "0" and "1" of bit data even if delay occurs.

[0009]

According to the present invention, the above-mentioned problem is solved by using a delay circuit for delaying data by one bit, a delayed nth bit data and a non-delayed (n + 1) th bit data. When the data of the nth bit and the data of the (n + 1) th bit have the same value, a signal with a duty ratio of zero in the 1-bit period is output, and when the data of the nth bit and the (n + 1) th bit are different, Is achieved by a signal output circuit that outputs a signal having a non-zero duty ratio in the 1-bit period and a data identification circuit that includes an identification circuit that identifies "0" and "1" of each bit data using the signal. .

[0010]

In the data discriminating circuit which represents "0" and "1" by the difference in duty ratio and discriminates the logical value of each bit data of the bit string in which the logical value of the leading bit is known, the data is delayed by one bit. , Nth bit and (n +
1) When the bit data has the same value, a signal with a duty ratio of zero is output, and when the data of the nth bit and the (n + 1) th bit are different, a signal with a nonzero duty ratio is output. Is used to determine whether the logical value of the current bit is the same as or different from the logical value of the immediately preceding bit, and "0" or "1" of each bit data is identified. With the above,
Even if there is a delay in the fall, the bit data will be
It is possible to distinguish between 0 "and" 1 ".

[0011]

【Example】

(a) Embodiment (a-1) Overall Configuration FIG. 1 is a configuration diagram of a data identification circuit according to the present invention. 11 is a bus identification circuit, and 21 is a bus input circuit (corresponding to the bus input circuit BUIC in FIG. 8). And the bus input circuit 21
9 to 9, signals having different duty ratios are input depending on "0" and "1" as shown in FIG. In the data identification circuit 11, 11a is a delay circuit that delays the signal output from the bus input circuit 21 by a time of one bit width (24 μs), 11b is an exclusive OR circuit, and the delayed nth bit signal The exclusive OR of the signals of the (n + 1) th bit that is not delayed is calculated, and the logical value (“0”, ”of the nth bit and the (n + 1) th bit is calculated.
1 ") have the same value, a signal with a duty ratio of zero during the 1-bit period is output, and if the data of the nth bit and the (n + 1) th bit differ, the duty ratio during the 1-bit period is not zero. Output a signal.

FIG. 2 is an explanatory diagram of output waveforms of the exclusive OR circuit 11b. As shown in FIG. 2A, the nth bit and the (nth)
When the +1) bit logical values ("0", "1") are different, a signal (duty ratio is not zero) DT having a high level period is output in the central portion, but (b), (c ), When the nth bit and the (n + 1) th bit have the same logical value, a 1-bit width low-level signal (duty ratio is zero) DT is output. Returning to FIG. 1, 11c is an exclusive OR circuit 11b in synchronization with the clock signal CLK.
A flip-flop 11d that holds the high level of the signal DT output from the flip-flop 11d is a clock generation unit that outputs a high-speed clock signal CLK and flip-flops a few clocks before the end of the 1-bit width, as shown in FIG. 11e, which outputs a read signal CL _RD for reading the set state of and a reset signal CL _RS for resetting the flip-flop immediately before the end of the 1-bit width, 11e
Is an AND gate, and 11f is a data processing unit.

(A-2) Data identification operation When the duty of the signal DT output from the exclusive OR circuit 11b is not zero, the flip-flop 11c is set by the high speed clock signal CLK after the rising of the signal (Q output Is "H"). On the other hand, the exclusive OR circuit 11
When the duty of the signal DT output from b is zero, the flip-flop 11c is not set (Q output is "
L ″). Then, the Q output of the flip-flop 11c is
Data read clock C generated before the end of 1 bit width
The data is read by L _RD and input to the data processing unit 11f. The data processing unit 11f determines that the logical value of the current bit is different from the logical value of the immediately previous bit when the read signal D is at the high level, and the logical value of the current bit is at the low level when the read signal D is at the low level. It is determined to be the same as the logical value.
In the format shown in FIG. 9, the second half of the SOM is 2
Since the waveform of 4 μs is the same as the waveform of “1”, the first bit can be regarded as “1”. Therefore, thereafter, by referring to whether the current bit is the same as or different from the immediately previous bit, it is possible to identify the logical values of all the bits that are sequentially bit serial.

After reading the state of the flip-flop, the flip-flop 11c is reset by the reset signal CL _RS generated immediately before the end of the 1-bit width, and thereafter the above-mentioned data reading is continued. According to such a data identification circuit,
Even if the fall of the signal output from the bus input circuit 21 is delayed, a signal with a non-zero / zero duty ratio is output according to the combination of the logical values of the n-th bit and the (n + 1) -th bit. It is possible to identify the logical value of each bit. Further, since the data read clock CL _RD is provided near the end of the 1-bit width, the logical value of each bit can be reliably identified even if the fall of the signal output from the bus input circuit 21 is delayed by a considerable amount.

(B) Alternative Configuration of Exclusive-OR Circuit In the embodiment shown in FIG. 1, when the exclusive-OR circuit is used and the data of the nth bit and the (n + 1) th bit have the same value, the duty ratio is increased. Outputs a signal of zero, and the nth bit and the (n +
1) When the bit data is different, a signal having a non-zero duty ratio is output, but a circuit other than the exclusive OR circuit can be used. FIG. 4 is another block diagram of such a signal output circuit. In the figure, reference numeral 50 is a signal output circuit, 51 is a polarity inverting unit that inverts the polarity of the signal output from the delay device 11a, and 52 is a delayed nth bit signal and a non-delayed (n + 1) th bit signal. Is an analog adder for adding in an analog manner, 53 is a polarity inverter for inverting the polarity of the analog adder output, and 54 is an OR gate. When the n-th bit is “0” and the (n + 1) -th bit is “1”, the output signal waveform of the analog adder 52 has a concave shape of −5 V at the center, as shown in FIG. The waveform is shown. Further, when the nth bit is "1" and the (n + 1) th bit is "0", the output signal waveform of the analog adder 52 is convex at + 5V at the center, as shown in FIG. 5B. Shows the waveform of. That is, when the logical values of the nth bit and the (n + 1) th bit are different, the signal waveform is concave or convex at the center. On the other hand, when the nth bit is “1”, the (n +
When the 1) bit is "1", the output signal waveform of the analog adder 52 is 0 V for the entire period of 1 bit as shown in FIG. 5 (c). Although not shown, the nth bit is "
0 "and the (n + 1) th bit is" 0 ", the output signal waveform of the analog adder 52 is 0 V for the entire 1-bit period.
Becomes That is, when the nth bit and the (n + 1) th bit have the same logical value, the waveform becomes flat and there is no unevenness.

Therefore, when the OR gate 54 having a predetermined logic level inverts the polarity of the output signal of the analog adder 52 and the logical sum of the output signal of the analog adder 52 are calculated, the nth bit and the nth bit are calculated. When the logical values of the (n + 1) th bit are the same value, the signal DT having a duty ratio of zero is output, and when the logical values of the nth bit and the (n + 1) th bit are different, the signal D having a nonzero duty ratio.
T is output. By inputting this signal DT to the flip-flop 11c of FIG. 1, it is possible to identify "0" and "1" of the bit data afterward, as in the case of FIG.
Although the present invention has been described above with reference to the embodiments, the present invention can be variously modified according to the gist of the present invention described in the claims, and the present invention does not exclude these.

[0017]

As described above, according to the present invention, "0" and "1" are represented by the difference in duty ratio, and the data identification circuit for identifying the logical value of each bit data of the bit string in which the logical value of the leading bit is known. In the case where the data is delayed by 1 bit, and the delayed nth bit data and the undelayed (n + 1) th bit data have the same value, a signal having a duty ratio of 0 is output and (N + 1)
If the bit data is different, a signal with a non-zero duty ratio is output, and the signal is used to determine whether the logical value of the current bit is the same as or different from the logical value of the immediately preceding bit, and the " Since it is configured to identify 0 "and" 1 ", it is possible to accurately identify" 0 "and" 1 "of bit data even if a delay occurs in the fall of the input signal.
Further, according to the present invention, it is possible to identify each bit data of the data string in which "0" and "1" are represented by the difference in duty ratio with a simple configuration using the exclusive OR circuit.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a data identification circuit of the present invention.

FIG. 2 is a waveform chart of an exclusive OR circuit output.

FIG. 3 is a signal waveform diagram of each part.

FIG. 4 is a configuration diagram of a signal output circuit.

FIG. 5 is a waveform diagram for explaining the operation of the signal output circuit.

FIG. 6 is an overall configuration diagram of an audio-visual system.

FIG. 7 is an explanatory diagram of connection between units.

FIG. 8 is a configuration diagram of a bus driver.

FIG. 9 is an explanatory diagram of a data format.

FIG. 10 is an explanatory diagram of waveforms of SOM, “0”, and “1” bits.

FIG. 11 is an explanatory diagram of a conventional data identification method.

[Explanation of symbols]

 11 ... Data identification circuit 11a ... Delay device 11b ... Exclusive OR circuit 11c ... Flip-flop 11d ... Clock generation unit 11f ... Data processing unit 21 ... Bus input circuit

Claims (2)

[Claims] 1. A data identification circuit for expressing "0", "1" by a difference in duty ratio and for identifying the logical value of each bit data of a bit serial data string in which the logical value of the first 1-bit data is known. , A delay circuit for delaying the data by 1 bit, and a delayed (n + 1) th signal that does not delay the nth bit signal
When the data of the nth bit and the data of the (n + 1) th bit have the same value using the signal of the bit, a signal having a duty ratio of 0 in the 1-bit period is output, and the nth bit and the (n + 1) th bit are output.
A signal output circuit that outputs a signal having a non-zero duty ratio in a 1-bit period when the bit data is different, and a discrimination circuit that discriminates "0" and "1" of each bit data using the signal are provided. A data identification circuit characterized by the above. 2. The signal output circuit is an exclusive OR circuit for performing an exclusive OR operation on the delayed nth bit data and the undelayed (n + 1) th bit data. 1. The data identification circuit described in 1.