JPH05130088A - Data communication system and transmission speed setting circuit - Google Patents

Abstract

PURPOSE:To realize the data communication system and the transmission speed setting circuit in which the transmission speed is made variable through one communication line. CONSTITUTION:The half duplex start-stop serial transmission is implemented by using a communication line H, and an IC card 5 superimposes a transmission speed setting pulse to the stop bit of transmission data to inform the revision of the transmission speed. A transmission speed setting circuit 1 uses a switch circuit 15 so as to distribute the transmission data flow and extracts a superimposed transmission speed setting pulse WB and varies a frequency division signal D accordingly to vary the period of a sampling signal, then the tracing of the transmission speed is attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication system and a transmission speed setting circuit, and more particularly, to a data communication system in which the transmission speed is dynamically set by a half-duplex start / stop serial transmission system, and The present invention relates to a transmission rate setting circuit for setting the transmission rate.

[0002]

2. Description of the Related Art The asynchronous serial transmission system is a kind of communication system for serially transmitting and receiving a plurality of bits of data and requires a small number of communication paths.
With the spread of the C standard and the serial interface IC, it has been widely used in the area of relatively low speed communication and data transmission, for example, data communication via a telephone line and communication between personal computers. Although this half-duplex start / stop type serial transmission method is already generally known,
Briefly, since it is half-duplex, one communication path transmits data from the first device to the second device at one time, and at the other time, from the first device to the second device. Two-way communication is performed by transmitting data to.

Furthermore, since it is a start-stop synchronization method, it does not share a synchronization signal such as a clock, and the first and second devices perform processing by their respective clocks, and since it is serial transmission, a plurality of bits of data are transmitted one bit at a time. It is transmitted and received as bit string data that is consecutive in order. However, a start bit is inserted immediately before the bit string data for synchronization, and one or two stop bits at a different level from the start bit are added to the end of the bit string data in order to clarify the next other start bit. Added to. A parity bit may be inserted immediately before the stop bit to detect a transmission error.

[0004]

In the case of performing communication by the above-mentioned start-stop synchronization type serial transmission method, conventionally, the first and second devices are set and adjusted in advance so that the transmission speeds match each other. It is usually set. Further, in the case where the transmission rate is variable as necessary, conventionally, the signal line other than the communication path is used to transmit the information for changing the transmission rate. By the way, in order to reduce the size of the built-in microcomputer such as a non-contact type IC card,
Further, in order to reduce the number and size of communication drivers and coils, a device having only one signal line for data input / output cannot change the transmission speed by the same method as the conventional one.

However, at the stage of standardizing the communication protocol of the IC card, the concept of making the transmission rate variable appears, and it is necessary to deal with this. As one method of varying the transmission rate in a device having only one signal line for data input / output, a method of associating transmission rate change information with a specific value of transmission data can be considered. In this method, there is a restriction that the specific value cannot be directly transmitted / received, and therefore, there is a problem that a circuit or means for processing the transmission data becomes complicated. An object of the present invention is to solve such a problem, and to provide a data communication system capable of varying the transmission speed in one communication path without sacrificing the transmission data, and the data communication method. It is to realize a transmission speed setting circuit that makes a communication system a reality.

[0006]

The configuration of the data communication system of the present invention which achieves such an object is a first device having a first signal line for data input / output and a first device for data input / output. A second device having two signal lines; and a communication path communicating between the first signal line and the second signal line.
Is a data communication system in which the first device and the second device exchange data with each other by half-duplex start / stop serial transmission via the signal line, the communication path, and the second signal line. ,
Transmission in which one of the first device and the second device superimposes a transmission rate setting pulse having a pulse width shorter than the pulse width of the stop bit on the stop bit when changing the transmission rate to another predetermined transmission rate. The other one of the first device and the second device has a speed setting pulse generating means, monitors the stop bit, and determines a subsequent transmission speed according to the transmission speed setting pulse superposed on the stop bit. The pulse is changed to the predetermined transmission rate set by this pulse.

Further, the structure of the transmission rate setting circuit of the present invention for realizing such a data communication system is a communication path for communicating data with a first device such as an IC card by half-duplex start / stop serial transmission. A first signal line for inputting and outputting data, a second signal line for inputting data by an asynchronous synchronization type serial transmission from a second device such as an IC card reader / writer, and an asynchronous synchronization to the second device. The third signal line for outputting data by the serial transmission, the division ratio signal and the basic clock from the second device are received, and the basic clock is divided by the division ratio indicated by the division ratio signal. Thus, the sampling signal generating circuit that generates the sampling signal corresponding to the transmission speed and outputs the sampling signal to the second device, the first terminal is connected to the first signal line, and the second terminal is connected to the second signal line. The third terminal is connected to the first Via chromatography preparative circuit (or directly) 3
Switch circuit connected to the signal line and the sampling signal generation circuit for controlling the switch circuit when receiving the first transmission data signal from the first signal line to connect the first terminal and the third terminal. To the phase of the sampling signal and receives the second transmission data signal from the second signal line to control the switch circuit to control the first
A switch control circuit for connecting the first terminal and the second terminal to each other and controlling the switch circuit when the signal from the sampling signal generating circuit is received to disconnect the first terminal from the second and third terminals; A window for receiving a signal corresponding to the timing of the stop bit of the first transmission data from the sampling signal generation circuit and generating a window pulse having a pulse width included in the stop bit and including a transmission speed setting pulse A pulse generating circuit, receiving the window pulse and the first transmission data,
A second gate circuit for extracting and outputting a transmission rate setting pulse superimposed on the stop bit in order to notify that the first apparatus changes the transmission rate to another predetermined transmission rate; and the transmission rate setting pulse. And a frequency division ratio setting circuit that outputs the frequency division ratio signal corresponding thereto to the sampling signal generation circuit.

[0008]

According to the data communication system of the present invention having such a configuration, there is only one communication path between the first device and the second device and no other communication means is provided. Since the data transmission modification pulse is transmitted while being superposed on the stop bit, all the data bits can be used for any purpose without any restriction. Moreover, when one of the first device and the second device changes its own transmission rate, the transmission rate setting pulse is superposed on the stop bit, transmitted, and then transmitted. Since the other of the first device and the second device changes its subsequent transmission rate according to the transmission rate setting pulse superimposed on the stop bit, the first apparatus and the second apparatus
Both can switch to the same new transmission rate. Therefore, the communication can be normally continued even after the transmission speed is changed.

Further, in the transmission speed setting circuit of the present invention, first, when data is transmitted from the second device such as an IC card reader / writer to the first device such as an IC card, a second device is used. The switch control circuit that receives the second transmission data signal from the device controls the switch circuit to connect the first terminal and the second terminal, so that the second transmission data signal is the second signal. Line, switch circuit, first signal line,
It is transmitted to the first device via the communication path in order. Then, at the timing of the transmission end, the switch control circuit which receives the signal from the sampling signal generating circuit controls the switch circuit to disconnect the first terminal from the second terminal, so Once the data transmission to one device is finished (due to the end of the stop bit), the next data transmission can be dealt with. In addition, the transmission speed of the asynchronous serial transmission is about 19200 baud at most (about 52 μm).
s / bit), so long as the operating speed of the electronic switch circuit is set, there is no inconvenience even if the switch circuit is controlled after receiving the transmission data signal.

Next, from the first device such as an IC card, the IC
The case of transmitting data to a second device such as a card reader / writer will be further described depending on the presence or absence of a transmission speed setting pulse. When the stop bit of the first transmission data signal does not include the transmission speed setting pulse, the switch control that receives the first transmission data signal from the first device through the communication path and the first signal line. The circuit controls the switch circuit to connect the first terminal and the third terminal, so that the first transmission data signal is transmitted through the communication path, the first signal line,
It is transmitted to the second device through the switch circuit and the third signal line in this order. Further, at the end of the transmission after the end of the stop bit, the first terminal and the third terminal are disconnected, and the next data transmission can be dealt with, as in the case described above.

Finally, the case where the stop bit of the first transmission data signal includes the transmission speed setting pulse will be described. As described above, the first transmission data signal is transmitted to the second device through the communication path, the first signal line, the switch circuit, and the third signal line in this order. Further, the transmission rate setting pulse is extracted from the stop bit of the first transmission data signal using the window pulse, and the frequency division ratio setting circuit receiving the transmission rate setting pulse sets the frequency division ratio according to the transmission rate setting pulse. change. This frequency division ratio is used as a frequency division ratio when the basic clock is frequency-divided and the sampling signal is generated. Therefore, thereafter, the frequency of the sampling signal that determines the transmission rate in the second device is determined. Will change. In this way, when the first device changes its own transmission speed and is notified to the second device by superimposing the transmission speed setting pulse on the stop bit, the transmission speed setting circuit of the present invention notifies it. Since the period of the sampling signal after the detection is changed, it is possible to follow the transmission speed of the second device so as to match that of the first device.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An IC card and its reader / writer as an embodiment of the data communication system and transmission rate setting circuit of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration of an IC card and its reader / writer according to an embodiment of the present invention.
FIG. 2 shows an example of the data format of the asynchronous serial transmission system and the waveform of the sampling signal. FIG. 3 is a waveform example of a stop bit on which a transmission rate setting pulse is superimposed. FIG. 4 shows another stop bit waveform example. In order to avoid a complicated description, a signal line and a signal on the line will be described with the same reference numeral when it is clear from the description.

In FIG. 1, 5 is an IC card as a specific example of the first device, 2 is a microcomputer provided in the IC card, 2a is transmission rate setting pulse generating means by a microcomputer, and 2b is a start-stop synchronous series. Serial transmission means 2c for controlling transmission is a driver receiver for the communication path H. Further, 4 is a reader / writer as a specific example of the second device, 3 is a reader / writer main body having separate transmission and reception signal lines, and 1 is a transmission speed setting circuit incorporated in the reader / writer. Further, in the transmission rate setting circuit 1, 11 is a sampling signal generating circuit, 12 is a window pulse generating circuit, 13 is a frequency division ratio setting circuit, 14 is a switch control circuit, 15 is a switch circuit, 16 and 17 are gate circuits, 2c. Is a driver receiver for the communication path H. The terminals 15a, 15b and 15c are specific examples of the first, second and third terminals, respectively.

First, the communication path H in FIG. 1 will be described. Although it is abbreviated with one line in the figure, since an IC card is taken as an example here, the IC card 5 is normally inserted into the reader / writer. As a result, the communication path H is established by magnetic coupling or optical coupling. At this time, the non-contact type IC card may be limited to one communication path due to various restrictions. Further, the signal lines B and C for data input / output are not directly connected to the communication path,
Usually, driver receivers 1a, 2c suitable for the coupling medium
Connected via.

Next, the structure of the IC card 5 will be described. Normally, the IC card 5 is a micro-card for managing and updating data in a memory (not shown) through communication with the reader / writer 4. The computer 2 is provided. For the communication, the microcomputer 2 has a transmission speed setting pulse generating means 2a and a serial transmission means 2b, and inputs and outputs transmission data via a data input / output signal line C. Again, due to the portability and cost of the IC card, it is necessary to reduce the size of the microcomputer, and the number of signal lines C for data input / output is often saved to one. A half-duplex start-stop synchronous serial transmission method will be adopted, which requires less.

Explaining the structure of the reader / writer side, it is roughly composed of a reader / writer main body 3 and a transmission speed setting circuit 1 incorporated on the communication path side thereof. The reader / writer 3 has an output line for data transmission ( SD (see SD) and input line (see RD) are separately provided, and the basic clock CK is output to input the sampling signal S corresponding to the transmission speed. Data communication can be performed by the interface IC, so detailed description will be omitted.

In the transmission speed setting circuit 1, the signal line B is connected to the communication line H via the driver receiver 1a corresponding to the communication medium, the signal line SD is connected to the output line of the reader / writer 3 for data transmission, and the signal The line RD is connected to the input line for data transmission of the reader / writer 3. The sampling signal generation circuit 11 receives the basic clock CK and divides it by the frequency division ratio indicated by the frequency division ratio signal D to generate a sampling signal S corresponding to the transmission speed and supply it to the reader / writer 3. .. Therefore, if the frequency division ratio is changed, the transmission speed of the reader / writer 3 is changed.

In the switch circuit 15, the terminal 15a is connected to the signal line B, the terminal 15b is connected to the signal line SD,
Gate circuit 1 whose terminal 15c receives the window pulse W
It is connected to the signal line RD via 7. The switch control circuit 14, when there is a transmission data signal on the signal line B,
In other words, when the start bit is generated, the start bit is detected, the switch circuit 15 is controlled, the terminals 15a and 15c are connected, and the transmission data is transmitted through the signal line RD.
To send to. On the contrary, when there is a transmission data signal on the signal line SD, the terminals 15a and 15b are connected to send the transmission data to the signal line B. This converts half-duplex and full-duplex at the circuit level. Then, a signal indicating that the transmission data is received is sent to the sampling signal generation circuit 11.

Upon receiving the output from the switch control circuit 14, the sampling signal generation circuit 11 initializes the phase of the sampling signal. In addition, the timing is measured according to the current transmission speed, and the stop bit generation is completed. In response to this, a signal indicating the timing of ending the connection at the switch 15 is generated and output to the switch control circuit 14. At this time, the sampling signal generation circuit 11 further generates a signal indicating the generation timing of the stop bit and outputs it to the window pulse generation circuit 12. When the window pulse generation circuit 12 receives the output from the sampling signal generation circuit 11, the window pulse W having the pulse width included in the stop bit of the corresponding transmission data and including the transmission speed setting pulse (see FIG. 3). ) Occurs.

The gate circuit 16 receives the window pulse W and the transmission data on the signal line B (see FIG. 3), extracts the stop bit of this transmission data, and superimposes the transmission speed setting pulse WB (FIG. 3). Reference) and outputs it to the frequency division ratio setting circuit 13. The frequency division ratio setting circuit 13
Upon receiving the transmission rate setting pulse WB, the frequency division ratio is maintained or increased or decreased according to the number of pulses or the code (01, 10, 11, etc.) indicated by the waveform, and the frequency division ratio signal D is sent to the sampling signal generation circuit 11. Is output as.

The procedure of communication between the IC card 5 having such a configuration and the reader / writer 4 will be described below. IC card 5
Is inserted in the reader / writer 4, and the communication path H is already established. Then, under the condition that the transmission speed is constant, the IC card 5 and the IC card 5 are transmitted through the signal line C, the driver receiver 2c, the communication path H, the driver receiver 1a, and the signal line B by the half-duplex start / stop serial transmission. Communication with the reader / writer 4 is possible. This has been conventionally done, but it will be briefly described with reference to the waveform example of FIG. The waveform example of RD is an example showing the data format in the serial transmission system. In this case, the data of 8 bits (DB portion), the parity bit PB, and the stop bit STP of 1 bit is the microcomputer 2 It has just arrived at the signal line RD.
Since it is a start-stop synchronization method, each bit of serial data is read at the falling timing of the sampling signal S synchronized with the start end of the start bit SB.

Next, the procedure for changing the transmission rate, which is the main point of the present invention, will be described. In the IC card 5, when changing the transmission rate, the transmission rate setting pulse generating means 2a generates transmission rate setting pulses having different pulse numbers depending on whether the transmission rate is increased or decreased. Then, the serial transmission means superimposes the transmission speed setting pulse on the stop bit of the transmission data in the data format of the serial transmission method, and outputs the pulse. This transmission data is transmitted to the signal line B via the communication path H. The pulse width of the transmission speed setting pulse is smaller than the pulse width of the stop bit, and if possible, ½ or less thereof is preferable.

Since the transmission speed setting pulse is superposed on the stop bit of the transmission data B on the signal line B, when the transmission data B and the window pulse W generated in response thereto are passed through the gate circuit 16. , The transmission speed setting pulse WB is extracted (see the waveform example in FIG. 3). Then, the frequency division ratio setting circuit 13 increases or decreases the frequency division ratio according to the number of the transmission speed setting pulses WB or the code indicated by the waveform thereof, so that the period of the subsequent sampling signal is changed, whereby the sampling signal is changed. A sampling signal S having a cycle corresponding to the transmission speed is sent from the generation circuit 11 to the reader / writer body 3. As a result, the transmission speed of the reader / writer 4 follows the transmission speed of the IC card 5.

The flow of transmission data between the reader / writer 3 and the signal line B in the case where the transmission speed setting pulse is not superimposed is apparent from the description of the configuration of the switch control circuit 14, but the transmission speed setting pulse is set. When the pulses are superimposed, the transmission data B and the window pulse W are combined by passing through the gate circuit 17, and the transmission data B is transmitted.
Stop bits are restored to the canonical data format. Therefore, a standard serial interface IC can be used for the reader / writer body 3. Here, the gate circuit 17 can be omitted if the standard serial interface IC is not used, and the terminal 15c and the signal line RD are directly connected.

Further, the transmission rate setting pulse in the waveform example of FIG. 3 has a pulse number of 2, but as long as the transmission rate of the communication path H permits, as in the waveform example of FIG. It may be. Furthermore, the unit of increase / decrease is not limited to doubling and halving, but may be quadruple, etc., and the correspondence with the number of pulses is also arbitrary, as long as it is unified among the communicating devices. In this embodiment, only the reader / writer 4 is provided with the transmission speed setting circuit 1 so as to follow the transmission speed of the IC card 5. However, in order to avoid a complicated explanation, this simplifies the circuit configuration. The IC
If the card 5 also includes the transmission rate setting circuit, it is possible to mutually follow the notification of the transmission rate change of the other party.

[0026]

As can be understood from the above description, in the data communication system using the transmission rate setting circuit of the present invention, by superimposing the transmission rate setting pulse on the stop bit, the transmission is performed at the circuit level. You can change the speed. As a result, there is an effect that it is possible to realize a data communication system and a transmission rate setting circuit capable of varying the transmission rate in one communication path without sacrificing the transmission data.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an IC card and its reader / writer according to an embodiment of the present invention.

FIG. 2 is a waveform example of a data format of a start-stop synchronization type serial transmission system and a sampling signal.

FIG. 3 is a waveform example of a transmission rate setting pulse and a stop bit on which the pulse is superimposed.

FIG. 4 is a waveform example of another stop bit on which a transmission rate setting pulse is superimposed.

[Explanation of symbols]

1 ... Transmission speed setting circuit, 2 ... Microcomputer, 2
a ... Transmission speed setting pulse generating means, 2b ... Serial transmission means, 2c ... Driver receiver, 3 ... Reader / writer main body,
4 ... Reader / writer, 5 ... IC card, 11 ... Sampling signal generating circuit, 12 ... Window pulse generating circuit, 1
3 ... Dividing ratio setting circuit, 14 ... Switch control circuit, 15 ...
Switch circuits, 16, 17 ... Gate circuits, 2c ... Driver receivers, 15a, 15b, 15c ... Terminals.

Claims (2)

[Claims] 1. A first device having a first signal line for data input / output, a second device having a second signal line for data input / output, a first signal line and a second signal line. A communication path that may communicate with the signal line, and via the first signal line, the communication path, and the second signal line,
A data communication method in which a first device and a second device exchange data with each other by half-duplex start / stop serial transmission, and one of the first device and the second device has a transmission rate. Has a transmission rate setting pulse generating means for superimposing a transmission rate setting pulse having a pulse width shorter than the pulse width of the stop bit on the stop bit when changing to another predetermined transmission rate, the first device and the second device. The other one of the devices monitors the stop bit and changes the subsequent transmission rate to the predetermined transmission rate set by this pulse according to the transmission rate setting pulse superimposed on the stop bit. And data communication method. 2. A first signal line for data input / output for communicating with a communication path for communicating data with a first device such as an IC card by half-duplex asynchronous serial transmission, an IC card reader / writer, etc. A second signal line for inputting data by the asynchronous serial transmission from the second device, a third signal line for outputting data by the asynchronous serial transmission to the second device, and a frequency division ratio signal. A sampling signal for receiving a basic clock from the second device and dividing the basic clock by the frequency division ratio indicated by the frequency division ratio signal to generate a sampling signal corresponding to the transmission speed and outputting the sampling signal to the second device. Generating circuit, first
The terminal of is connected to the first signal line, the second terminal is connected to the second signal line, and the third terminal is (or directly) connected to the third signal line via the first gate circuit. And a switch circuit, which receives the first transmission data signal from the first signal line, controls the switch circuit to connect the first terminal and the third terminal, and sends a signal to the sampling signal generating circuit. When the phase of the sampling signal is initialized and the second transmission data signal is received from the second signal line, the switch circuit is controlled to connect the first terminal and the second terminal to output the signal from the sampling signal generation circuit. Upon receipt, a switch control circuit for controlling the switch circuit to disconnect the first terminal from the second and third terminals, and a signal corresponding to the stop bit timing of the first transmission data from the sampling signal generating circuit. And a window pulse generating circuit for generating a window pulse for extracting a transmission rate setting pulse from the stop bit, and a first device which receives the window pulse and the first transmission data sets the transmission rate to another predetermined transmission rate. A second gate circuit for extracting and outputting a transmission rate setting pulse superimposed on the stop bit in order to notify that the change is made to the stop bit, and the frequency division ratio signal corresponding to the transmission rate setting pulse for the sampling signal. And a frequency division ratio setting circuit for outputting to a generation circuit.