JP3434615B2 - Signal transmission system and transmission device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission system and a transmission device, and more particularly to reduction of transmission lines between transmission devices in signal transmission.

[0002]

2. Description of the Related Art As a method of serial transmission of signals, there is, for example, RS-232C. With such serial transmission, full-duplex communication can be performed between the data terminal equipment (DTE) and the data circuit terminating equipment (DCE) under the interface condition of JIS-X-5101, for example.

Between the data terminal device and the data line terminating device, in addition to transmission and reception of transmission data and reception data,
The transmission signal element timing signal and the reception signal element timing signal must be transmitted as clocks respectively synchronized with these transmission data and reception data.

In addition, even when high-speed data and low-speed data are transmitted and received between transmission devices, if the synchronized high-speed clock and low-speed clock are not transmitted together with the respective data, the receiving side It was not possible to play high speed data or low speed data.

[0005]

However, as the number of types of data transmitted and received between transmission devices at different speeds increases, a clock synchronized with these data must also be transmitted. The number of signal wires between devices is large, wiring work is complicated, and the number of connecting pins of the connecting connector is large, the connecting connector is large,
There was a problem such as increasing the size of the device.

Further, when the number of clock lines of various speeds between transmission devices increases, the influence of electromagnetic interference (electromagnetic interference: EMI) increases, and the radiation noise from the clock lines increases, which causes the noise to be superimposed on other data lines. Or cause unnecessary noise to be mixed into the transmission device, which may cause malfunction, or if shield measures are taken to prevent the effects of such electromagnetic interference, the signal cable may become thick, and the transmission device may be large and heavy. There are also problems such as getting tired.

Furthermore, in order to solve the above problems, it is conceivable that a plurality of data having different speeds are not transmitted in parallel but transmitted in a multiplexed manner, and various data are multiplexed. It is conceivable to send it with a multiplexing circuit and separate it with a demultiplexing circuit on the receiving side. However, it is not easy to manufacture a multiplexing circuit or a demultiplexing circuit, and in particular, it takes a lot of design man-hours because signals of various different speeds are multiplexed and demultiplexed. In addition, since a high-speed signal is transmitted to the line that transmits the multiplexed signal by multiplexing, the line is burdened and very high reliability is required. Since there are various problems as described above,
It was very difficult to take the optimum measure.

From the above, when transmitting a plurality of signals at different speeds between transmission devices, the number of wirings can be reduced and the circuit configuration of the transmission device can be increased with a simpler structure than the conventional one. It is required to provide a signal transmission system and a transmission device capable of reducing electromagnetic interference and transmitting various signals.

[0009]

Therefore, the present invention is directed to the first aspect of the present invention.
Is a signal transmission system for transmitting a plurality of signals at different signal speeds between the second transmission device and the second transmission device, and specifically, the first transmission device is the fastest F from among the plurality of signals. Generates a reference clock a for transmitting the signal A of
Reference clock generating means for outputting the reference clock a for the second transmission device, first transmitting means for transmitting the signal A of the fastest F in synchronization with the reference clock a, and among the plurality of signals. 1 or 2 or more clocks b for transmitting the remaining 1 or 2 or more signals B except the signal A of the fastest F
Of the reference clock a and a second transmitting means for transmitting the remaining one or more signals B in synchronization with the one or more clocks b. Equipped with.

Further, according to the present invention, the second transmission device receives the reference clock a from the first transmission device,
First receiving means for taking in the transmission signal A of the fastest F from the transmission device of No. 1 using the reception reference clock a, and one or more transmission signals B from the first transmission device from the reception reference clock a. Second clock generation means for generating one or more clocks c for fetching;
The above-described problem is solved by providing a receiving circuit including a second receiving unit that takes in one or more transmission signals B from the first transmission device by using the clock c described above.

[0011]

According to the configuration of the signal transmission system of the present invention, the reference clock generated by the reference clock generating means of the first transmission device is synchronized with the signal A of the fastest F, and at the same speed, The speed relationship may be higher than that.
By using such a reference clock a for transmission / reception processing in the first transmission device and also supplying it to the second transmission device, the reference signal of one reference signal generation circuit is used by both devices. It is configured to be shared.

That is, the signal A of the fastest F is transmitted in synchronization with the reference clock a, and one or more low-speed signals B other than the fastest F are transmitted in synchronization with one or more clocks b. The second transmission device takes in the transmission signal A in synchronization with the received reference clock a. Furthermore, one or more clocks c are generated from the received reference clock a,
Since one or more transmission signals B are fetched in synchronization with the clock c, each transmission signal can be received without the conventional clock transmission for each transmission speed, and the transmission signal line can be greatly reduced. Can be planned. Moreover, it can be easily realized mainly by configuring the clock generating means in the device. From the above, the above problems can be solved.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of the communication system of this embodiment. In FIG. 1, the communication system includes a high-speed transmission line (for example, about 256 kbit / s) for transmitting user data, mainly between the communication device 1 and the communication device 2.
Low-speed transmission for transmitting setting / monitoring data (for example, 1 kb
It / s) line and a reference clock (speed synchronized with the high-speed transmission signal) line. In addition, the communication device 1 outputs the transmission data SD to the line,
Take in the received data given from the line. On the other hand, the communication device 2 takes in the reception data RD from a plurality of terminals,
In addition, the transmission data SD can be given to these terminals.

A characteristic of this communication system is that, in performing high-speed transmission and low-speed transmission, only the reference clock is transmitted as the clock transmission.
Moreover, this reference clock is transmitted as a reference clock synchronized with a high-speed transmission signal. Further, this reference clock is transmitted so as to be given from the communication device 1 to the communication device 2 and is not transmitted from the communication device 2 to the communication device 1, and full duplex is provided for each of the high speed transmission and the low speed transmission. It is configured to realize communication.

The communication device 1 includes a reference clock generation circuit 11
, Serial input / output circuits (SIO) 12, 15 and CP
U13 and 16, n frequency dividing circuit 14, interface drivers 17, 18 and 20, and interface receiver 1
It is composed of 9 and 21.

The reference clock generation circuit 11 generates a reference clock synchronized with the high speed transmission signal. For example, assuming that the high speed transmission signal is 256 bit / s,
This reference clock is, for example, 256 kHz, and this reference clock is used for data transmission in the communication device 1.
The interface driver 17 is used so that it can be used by the communication device 2 while being used for data reception, and is supplied to the communication device 2 through the transmission line from here.

The serial input / output circuit 12 transmits the reference clock from the reference clock generation circuit 11 to the transmission clock TC.
K and the reception clock RCK. Further, the received data from the high speed transmission line is transferred to the receiving clock R.
It is taken in through the interface receiver 19 in synchronization with CK and given to the CPU 12. Furthermore, the serial input / output circuit 12 transmits the transmission data SD from the CPU 13 from the interface driver 18 in synchronization with the transmission clock TCK.

The CPU 13 is specifically a microprocessor MP, a program ROM, a work memory RAM.
And receive the received signal RD from the line,
Conversely, the transmission data SD is output to the line, and the signal fetched from the line is transmitted to the serial input / output circuit 12 by the transmission data S.
Give as D. On the other hand, it receives the reception signal RD from the serial input / output circuit 12.

The n frequency dividing circuit 14 is composed of a counter circuit, a gate circuit, etc., takes in the reference clock (for example, 256 kbit / s) from the reference clock generating circuit 11, and is required for low speed transmission (for example, 1 kbit / s). A low-speed transmission clock (for example, 1 kHz) is generated and given to the serial input / output circuit 15 as a reception clock and a transmission clock.

The serial input / output circuit 15 is an n frequency dividing circuit 1.
From 4 as the receiving clock RCK for low-speed transmission of data and the transmitting clock TCK, the receiving clock R
The data received from the interface receiver 21 is also captured in synchronization with CK and given to the CPU 16. Further, the serial input / output circuit 15 takes in the transmission data SD from the CPU 1 and supplies it to the interface driver 20, and the communication device 2
To low-speed transmission.

The CPU 16 is specifically a microprocessor MP, a program ROM, a work memory RAM.
And the like, and generates setting / monitoring data for transmitting / receiving setting / monitoring data of the apparatus to / from the communication apparatus 2 at low speed transmission (for example, about 1 kbit / s). This data is a setting for sending the internal setting state of the own device 1 as data, sending data for controlling the other communication device 2, and reading the operating state of the other communication device 2 from the data of the other communication device 2. It is monitoring data.

For this reason, the CPU 16 receives the received data RD from the communication device 2 in the low speed transmission and outputs it to the serial input / output circuit 15.
Take in from. Further, the setting state and the operating state in the own communication device 1 and the control contents of the partner communication device 2 are converted into information, which is given to the serial input / output circuit 15 as transmission data SD and transmitted at low speed to the communication device 2. .

(Communication device 2): The communication device 2 comprises a serial input / output circuit (SIO) 21, 25, a CPU 22,
26, an inverter 23, an n frequency dividing circuit 24, interface receivers 27, 28 and 30, and interface drivers 29 and 31.

The serial input / output circuit 21 receives a reference clock (for example, about 256 kHz) from the communication device 1 through the interface receiver 27 and a reception clock RC.
The reception data RD received as K and the transmission clock TCK and further transmitted at high speed (for example, 256 kbit / s) from the communication device 1 is taken in through the interface receiver 28 in synchronization with the reception clock RCK. Further, the transmission data SD from the CPU 22 is transmitted in synchronization with the transmission clock TCK, and is transmitted at high speed to the communication device 1 through the interface driver 29.

The CPU 22 is specifically a microprocessor MP, a program ROM, a work memory RAM.
The received data RD from the serial input / output circuit 21 is taken in, demultiplexed and output to a plurality of terminals, and the signals taken in from a plurality of terminals are multiplexed and given to the serial input / output circuit 21 as transmission data SD. It is a thing.

The inverter 23 takes in the reception reference clock received from the communication device 1 through the interface receiver 27, inverts its phase, and supplies it to the n frequency dividing circuit 24. As a result, the reference clock and the inverted clock can be out of phase with each other by 1/2 cycle. The clock whose phase is inverted in this way is given to the n frequency dividing circuit 24 in order to make the timing of fetching the reception data received from the communication device 1 by low-speed transmission accurate and to demodulate the data with high accuracy.

The n frequency dividing circuit 24, when supplied with a phase inversion clock (for example, about 256 kHz) from the inverter 23, synchronizes with a clock (for example, about 1 kbit / s) that is transmitted / received by low-speed transmission. (For example, about 1 kHz), and the serial input / output circuit 25 receives the transmission clock TCK and the reception clock RC.
It is given as K.

The serial input / output circuit 25 is an n frequency dividing circuit 2
The divided clock from 4 is used as the transmission clock TCK and the reception clock RCK, and the reception data RD by low-speed transmission is synchronously fetched. Also, the transmission clock TCK
In synchronization with the above, the setting / monitoring data (for example, about 1 kbit / s) from the CPU 26 is transmitted to the communication device 1 through the interface driver 31 as the transmission data SD.

The CPU 26 is specifically a microprocessor MP, a program ROM, a work memory RAM.
And the like, and generates setting / monitoring data for transmitting / receiving setting / monitoring data of the apparatus to / from the communication apparatus 1 at low speed transmission (for example, about 1 kbit / s). This data is a setting for sending the internal setting state of the own communication device 2 as data, sending data for controlling the other communication device 1, and reading the operating state of the other communication device 1 from the data of the other communication device 1. -It is monitoring data.

For this reason, the CPU 26 receives the received data RD from the communication device 1 in the low speed transmission to the serial input / output circuit 25.
Take in from. In addition, the setting state and operating state of the own communication device 2 and the control contents of the partner communication device 1 are converted into information, which is given to the serial input / output circuit 25 as transmission data SD and transmitted at low speed to the communication device 1. .

(System Operation): The operation of the communication system of FIG. 1 will be described with reference to the operation timing chart of FIG. In the explanation of this operation, the n divider circuit 1
The frequency division ratio n of 4 and 24 is set to 3 for simplicity, the frequency of the reference clock is 300 kHz, and the high-speed transmission rate is 300 kbi.
It is assumed that the transmission speed is t / s and the low transmission speed is 100 kbit / s.

(Clock transmission, high-speed transmission): Therefore, first, the reference clock generation circuit 11 of the communication device 1 generates and outputs the reference clock as shown in S1 of FIG. 2, and transmits it to the communication device 2 through the interface driver 17. , The serial input / output circuit 12 in the communication device 1 and n
It is given to the frequency dividing circuit 14 and.

The CPU 13 gives the user data received from the line to the serial input / output circuit 12 as transmission data SD to the communication device 2, and this transmission data SD is S2 in FIG.
Is transmitted at the falling timing of the reference clock at the timing as shown in FIG. 3, is driven by the interface driver 18, and is transmitted to the communication device 2, for example, 300 kbit / s.
High speed transmission is possible.

On the other hand, a reference clock is given to the communication device 2 and received by the interface receiver 27, and this received reference clock is given to the serial input / output circuit 21 and the inverter 23. The serial input / output circuit 21 supplied with the reception reference clock receives the reception data RD of the high-speed transmission from the communication device 1 as the reception reference clock and the reception clock R.
The fetched reception data RD is given to the CPU 22 at the rising timing of CK.

Data from a plurality of terminals is sent to the CPU 2
2 is multiplexed as transmission data, and the transmission data SD from the CPU 22 is synchronized with the transmission clock TCK.
As shown in S3, the transmission data SD is transmitted at high speed at the falling timing of the reception reference clock.

The interface receiver 19 receives the transmission data SD by high-speed transmission from the communication device 2, and the reception data RD is fetched by the serial input / output circuit 12 at the rising timing of the reference clock, and C
It is given to the PU 13. This reception data RD is output to the line as transmission data SD.

As described above, full-duplex communication is established between the communication device 1 and the communication device 2 by supplying the reference clock synchronized with the high-speed transmission line from the communication device 1 to the communication device 2. Can be done. Moreover, the number of clock lines could be reduced compared to the conventional one.

Although the clock is not transmitted from the communication device 2 to the communication device 1, this is not the case.
This is because the transmission delay time between and is one-way and is less than 1/4 of the cycle of the reference clock (S1 in FIG. 2). That is,
For the communication device 1, when the transmission delay time becomes one-fourth of the cycle of the reference clock in one way, the transmission delay time becomes ½ of the cycle of the reference clock in a round trip, and the communication device 1 receives the reference clock (reception clock). ) Rising timing (reception data acquisition timing) and the arrival timing of the transmission data SD from the communication device 2 become the same, so that the reception data cannot be accurately acquired.

Therefore, the transmission delay time between the communication device 2 and the communication device 1 is required to be one way and less than 1/4 of the cycle of the reference clock.

(Low-speed transmission): Next, the operation of low-speed transmission from the communication device 1 to the communication device 2 will be described. The n-divider circuit 14 divides the reference clock by a division ratio of 3,
As shown in S4, the divided output is generated and output at the rising timing of the reference clock, and is supplied to the serial input / output circuit 15 as the reception clock RCK and the transmission clock.

When the setting / monitoring data from the CPU 16 is given as the transmission data SD, the serial input / output circuit 15 outputs the transmission data SD at the falling timing of the transmission clock TCK, and the communication device is transmitted at low speed through the interface driver 20. Give to 2.

Interface receiver 30 of communication device 2
Is the transmission data SD by the low-speed transmission from the communication device 1.
When (S5 in FIG. 2) is received, the serial input / output circuit 25
Give to. Here, the inverter 23 inverts the phase of the reception reference clock and supplies it to the n frequency dividing circuit 24. It should be noted that the phase inversion of the reception reference clock is performed in accordance with the change point timing of the reception data arriving at the communication device 2 due to the low-speed transmission and the reception timing of the reception data by the reception clock in the serial input / output circuit 25. At the same time,
In order to prevent the reception data RD from being taken in incorrectly, phase inversion, that is, 1 of the reference clock
The setup / hold time is guaranteed by shifting the reception timing by / 2 cycles.

The n frequency dividing circuit 24 divides the frequency by a frequency division ratio of 3, starts frequency division output at the rising timing of the input reception inverted clock, and outputs at any timing of S6 to S8 in FIG. It is applied to the input / output circuit 25.

Therefore, the serial input / output circuit 25 divides the received data RD from the communication device 1 (S5 in FIG. 2) by the frequency dividing clock generated by the n frequency dividing circuit 24 (S6 to S8 in FIG. 2).
Is taken in at the rising timing of and is given to the CPU 26. Further, the setting / monitoring data generated by the CPU 26 is transmitted from the serial input / output circuit 25 as the transmission data SD, as shown in FIG.
2 is transmitted at the timing of any of S9 to S11 of FIG. 2 in synchronization with the falling timing of any of the transmission clocks S6 to S8, is output from the interface driver 31, and is given to the communication device 1 by low-speed transmission. To be

In the communication device 1, the interface receiver 21 receives the data transmitted from the communication device 2 at low speed, and the serial input / output circuit 15 rises the divided clock (reception clock RCK) at the timing of S4 in FIG. It is taken in at a timing and given to the CPU 16.

By supplying the reference clock synchronized with the high-speed transmission line from the communication device 1 to the communication device 2 as described above, full-duplex communication by low-speed transmission between the communication device 1 and the communication device 2 is performed. Can be established. Moreover, the number of clock lines could be reduced compared to the conventional one.

Although the clock is not transmitted from the communication device 2 to the communication device 1, the clock is transmitted from the communication device 2 and the communication device 1.
This is because the low-speed transmission delay time between and is one-way and is less than 1/4 of the cycle of the reference clock (S1 in FIG. 2). In other words, for the communication device 1, when the transmission delay time becomes one-fourth of the cycle of the reference clock in one way, the transmission delay time becomes ½ of the cycle of the reference clock in the round trip, and the divided clock ( Reception clock, rising timing of S4 in FIG. 2 (received data acquisition timing)
Then, the transmission data SD (for example, S10 in FIG. 2) from the communication device 2 arrives at the same timing, and the reception data cannot be accurately captured.

Therefore, even in low-speed transmission between the communication device 2 and the communication device 1, the transmission delay time is required to be less than 1/4 of the cycle of the reference clock in one way.

(Effect of Embodiment) According to the configuration of the above embodiment, when the high speed transmission and the low speed transmission are performed between the communication devices 1 and 2 by the full-duplex communication system, respectively, it is conventionally 4
Although one clock line is required, in the embodiment, only one reference clock synchronized with the high speed transmission can be dealt with, so that the number of clock lines can be significantly reduced. Moreover, even if there is only one clock line, the clocks required for low-speed transmission are generated by the internal n frequency dividing circuits 14 and 24 from the reference clock, so data transmission and data reception for low-speed transmission are performed. Can also be done accurately.

Since the configuration is as shown in FIG. 1, the communication devices 1 and 2 are provided with only the n frequency dividing circuits 14 and 24, and the communication device 2 need not be provided with the reference clock generation circuit. The structure of the device is simplified because it is not necessary to synchronize the reference clock generation circuits between the devices.

Therefore, when transmitting a plurality of signals at different speeds between transmission devices, the number of wires is reduced and the electromagnetic interference is reduced without increasing the circuit configuration of the transmission device with a simpler structure than the conventional one. Therefore, it is possible to realize a signal transmission system and a transmission device capable of transmitting various signals.

(Other Embodiments) (1) In the above embodiments, full-duplex communication is performed for each of high-speed transmission and low-speed transmission, but one-way communication is used. Can be easily applied to. Further, since the reference clock generation circuit 11 may be provided in either one of the communication devices 1 and 2, the configuration is simple.

(2) In addition to high-speed transmission and low-speed transmission, if it is desired to perform medium-speed transmission, the n-divider circuits 14 and 24 should divide and generate the medium-speed clock required for medium-speed transmission. Can be achieved with. Therefore, it can be easily applied to a signal transmission of a plurality of different speeds of three or more with a simple configuration (3) Furthermore, the communication device 1 can be replaced by, for example, a multiplex transmission device, and the communication device can be replaced. 2 can also be replaced as a terminal multiplex expansion device for multiplexing the signals of a plurality of terminal devices multiplexed by the multiplex transmission device. Further, it can also be applied to communication between terminal devices.

(4) Furthermore, high-speed transmission is 256 kbi.
Although the reference clock is set to 256 kHz when t / s is set, it is possible to generate and transmit a reference clock larger than that for high-speed transmission, divide the frequency, and use it for signal transmission in addition to the above correspondence. . That is, it is also preferable to configure a frequency divider circuit between the reference clock and the serial input / output circuits 12 and 21.

(5) Further, the frequency division output is started at the rising edge of the clock, and the transmission data is output at the falling edge of the transmission clock. However, the same effect as described above can be obtained.

[0057]

As described above, the configuration of the present invention is a signal transmission system for transmitting a plurality of signals at different signal speeds between the first transmission device and the second transmission device. The transmitting circuit of the transmitting device of the present invention generates a reference clock a for transmitting the signal A of the fastest F from the plurality of signals, and outputs the reference clock a for the second transmitting device. A first transmitting means for transmitting the signal A of the fastest F in synchronization with the reference clock a, and the remaining one or more signals B except the signal A of the fastest F of the plurality of signals. 1 or 2 or more clocks b from the above-mentioned reference clock a, and a second clock that transmits the remaining 1 or 2 or more signals B in synchronization with the 1 or 2 or more clocks b. And a receiving circuit of the second transmission device, comprising: A first receiving means for receiving the reference clock a from the first transmission device and receiving the transmission signal A of the fastest F from the first transmission device by using the reception reference clock a; 1 or 2 for capturing one or more transmission signals B from one transmission device
Second clock generating means for generating the above clock c and second receiving means for taking in one or more transmission signals B from the first transmission device by using one or more clocks c It is a thing.

With such a configuration, when transmitting a plurality of signals at different speeds between transmission devices with a simple configuration, the number of wirings can be reduced and the circuit of the transmission device can be reduced with a configuration simpler than the conventional one. It is possible to realize a signal transmission system and a transmission device capable of transmitting various signals while reducing electromagnetic interference without increasing the configuration.

[Brief description of drawings]

FIG. 1 is a functional configuration diagram of a communication system according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of the communication system according to the embodiment.

[Explanation of symbols]

1, 2 ... Communication device, 11 ... Reference clock generation circuit, 1
2, 15, 21, 25 ... Serial input / output circuit (SI
O), 13, 16, 22, 26 ... CPU, 14, 24 ...
n divider circuit, 17, 18, 19, 20, 29, 31 ... Interface driver, 19, 21, 27, 28, 30
... interface receiver.

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 29/08 H04L 7/00 H04L 7/04

Claims (6)

(57) [Claims] 1. A signal transmission system for transmitting a plurality of signals at different signal speeds between a first transmission device and a second transmission device, wherein the first transmission device is one of the plurality of signals. Generates a reference clock a for transmitting the signal A of the fastest F from the second reference clock a.
The reference clock generating means for outputting for the transmission device, the first transmitting means for transmitting the signal A of the fastest F in synchronization with the reference clock a, and the signal A of the fastest F of the plurality of signals. First clock generating means for generating from the reference clock a one or more clocks b for transmitting the remaining one or more signals B except for, and in synchronization with the one or more clocks b. The second transmission device includes a transmission circuit including a second transmission unit that transmits the remaining one or more signals B, and the second transmission device receives the reference clock a from the first transmission device, A first receiving means for taking in the fastest F transmission signal A from one transmission device using the reception reference clock a; and one or more transmission signals B from the first transmission device from the reception reference clock a. One for capturing Second clock generating means for generating two or more clocks c, and second receiving means for taking in one or more transmission signals B from the first transmission device using the one or more clocks c A signal transmission system comprising a receiving circuit including the following. 2. The second transmission device further comprises a transmission circuit for transmitting a signal to the first transmission device, and the first transmission device transmits from the transmission circuit of the second transmission device. A signal transmission system further comprising a reception circuit for receiving a signal, wherein the transmission circuit of the second transmission device transmits a signal C of the fastest F in synchronization with the reception reference clock a. Means and fourth transmitting means for transmitting the remaining one or more signals D except the signal C of the fastest F among the plurality of signals in synchronization with the one or more clocks c. At the same time, the receiving circuit of the first transmission device includes third receiving means for receiving the transmission signal C of the fastest F from the second transmission device by using the reference clock a, and the one or more clocks b. One or more from the second transmission device using The signal transmission system according to claim 1, further comprising: a fourth receiving unit that receives the transmission signal D. 3. A transmission circuit for transmitting a plurality of signals at different signal speeds, wherein the transmission circuit has a reference clock a for transmitting a signal A of the fastest F from among the plurality of signals. For generating the reference clock a, first transmitting means for transmitting the signal A of the fastest F in synchronization with the reference clock a, and the fastest F of the plurality of signals. Clock generating means for generating from the reference clock a one or more clocks b for transmitting the remaining one or more signals B except the signal A, and in synchronization with the one or more clocks b. A second transmission means for transmitting the remaining one or two or more signals B, the transmission device. 4. The transmission device according to claim 3, further comprising a receiving circuit for receiving a plurality of signals having different signal speeds, the receiving circuit using the reference clock a and a signal C of the fastest F. First to capture
And a second receiving means for receiving one or more signals D by using the one or more clocks b. 5. A receiver circuit for receiving a plurality of signals having different signal speeds, the receiver circuit receiving a reference clock a and fetching a signal A of the fastest F using the reception reference clock a. First receiving means and one or more clocks c for taking in the remaining one or more signals B except the signal A of the fastest F of the plurality of received signals from the reception reference clock a. A transmission device comprising: a clock generating means; and a second receiving means for taking in one or more signals B by using one or more clocks c. 6. The transmission device according to claim 5, further comprising a transmission circuit for transmitting a plurality of signals having different signal rates, the transmission circuit synchronizing with the reception reference clock “a” at a maximum speed F. Of the remaining one or more signals D except the signal C of the fastest F among the plurality of signals in synchronization with the first transmitting means for transmitting the signal C of A transmission device comprising: a second transmission unit for transmitting.