JPH05100993A - Signal line sharing system - Google Patents

Abstract

PURPOSE:To share an interruption signal line by providing an interruption signal sending timing signal line on a system bus, time-division-multiplex-using the interruption signal line at an interruption signal line drive circuit and providing a demodulating circuit. CONSTITUTION:The interruption signal line drive circuit 9 synchronizes an asynchronous interruption generation factor(1) generating at a bus slave module 2 with an interruption signal sending timing signal 1f so as to make it possible to time-division use the interruption signal line 1e. Besides, the demodulating circuit 14 on a bus master 3 demodulate a shared interruption signal by adjusting it to the interruption signal sending timing signal 1f and specifies a bus slave module requiring an interruption service. Namely, the interruption service requirement generated at a bus slave (1) outputs the signal which is synchronized with the interruption sending timing 1f in a prescribed timing by the interruption signal line drive circuit 9 to the interruption signal line 1e by making a signal line 5 at the interruption factor 1 to be significant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal line sharing system such as an interrupt signal line, and more particularly to an interrupt process related to a bus architecture of a microcomputer system.

[0002]

2. Description of the Related Art FIG. 9 is a functional division drawing showing, for example, a conventional microcomputer system.
Is a system bus for performing data communication between divided functional modules, 2 are provided as many as necessary, and bus slave modules (or simply referred to as bus slaves) in charge of each function, 3 are respective bus slave modules It is a bus master that provides services to 2.

Next, the operation will be described. When the two bus slave modules (1) on the system bus 1 need to be serviced by the bus master 3 for some reason, the bus slave module (2) drives the interrupt signal line 1c assigned to itself. Bus master 3
Detects that there is a request for an interrupt service from the bus slave module (1) by driving the interrupt signal line 1c, and provides a service such as data transfer to the bus slave module (1) on the system bus 1. Start using another signal line group 1d. FIG. 10 shows the bus slave 2,
3 is an internal block diagram of the bus master 3, and when the bus slave 2 needs to be serviced by the bus master 3, the signal line 5 of the interrupt factor (1) is made significant, and the bus driver 6 makes the interrupt signal on the system bus 1 Drive line 1c. In the bus master, all interrupt signal lines on the system bus are connected to the interrupt control circuit 8 via the bus receiver 7, and the interrupt control circuit 8 drives the interrupt line 1c, that is, on the system bus 1. That the bus slave (1) has a request for interrupt service.
The bus master 3 can start the interrupt service to the bus slave 2 by translating and transmitting it so that the CPU inside can interpret it.

[0004]

Since the conventional interrupt method is configured as described above, interrupt signal lines are required for the number of bus slave modules requesting interrupt service, and compatibility and the like are taken into consideration. When the physical specifications of the system bus are not changed, the number of interrupt signal lines required for the system function cannot be obtained.

The present invention has been made in order to solve the above-mentioned problems, and can share a signal line connected to a plurality of bus slave modules and connect the shared signal line. The purpose is to obtain a signal line sharing method in which the number of bus slave modules is not limited.

[0006]

A signal line sharing system according to a first aspect of the invention provides an interrupt signal transmission timing signal line (an example of a timing signal line) on a system bus, and a bus slave module (of a slave processing unit). (Example) Timing signal for sending an interrupt signal (an example of timing signal)
An interrupt signal line driving circuit (an example of a driving unit) that generates an interrupt signal (an example of a driving signal) synchronized with
The interrupt signal line (an example of a shared signal line) is time-division multiplexed, and a bus master (an example of a master processing unit) demodulates an interrupt signal that is time-division multiplexed by a predetermined method ( By having an example of receiving means), the interrupt signal line is shared.

In the signal line sharing system according to the second aspect of the invention, a bus clock line (an example of a clock signal line) is provided on the system bus, and the bus clock is provided on the bus slave module (an example of a slave processing unit). An interrupt signal line drive circuit (an example of a drive unit) that generates an interrupt signal (an example of a drive signal) synchronized with the signal, and an interrupt mask register (an example of a prohibition unit) that inhibits the operation of the interrupt signal line drive circuit. An interrupt signal line (an example of a shared signal line) is used in a time division manner, and an interrupt processing program (an example of a processing unit) activated by an interrupt signal used in a time division manner in a bus master (an example of a master processing unit). By specifying the bus slave module that has issued the interrupt signal, the interrupt signal line is shared.

[0008]

In the first aspect of the invention, the interrupt signal line drive circuit (driving means) synchronizes the asynchronous interrupt generation factor generated in the bus slave module with the interrupt signal transmission timing signal, and uses the interrupt signal line in a time division manner. Make possible Further, the demodulation circuit (reception means) on the bus master demodulates the shared interrupt signal in accordance with the interrupt signal transmission timing signal, and specifies the bus slave module that requested the interrupt service.

In the second invention, the interrupt signal line drive circuit (driving means) outputs an asynchronous interrupt generation factor generated in the bus slave module in synchronization with the bus clock signal line and outputs the interrupt mask register ( Since the prohibiting means) detects that another bus slave module uses the shared interrupt signal line and prohibits the operation of its own interrupt signal line drive circuit (driving means), the plurality of bus slave modules Therefore, double driving for one interrupt signal line can be prevented. Further, the interrupt processing program (processing means) on the bus master specifies the bus slave module that requested the interrupt service.

[0010]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, since 1 to 3 have been described above, they are omitted. 1f is an interrupt transmission timing signal line, and 1e
Is a shared interrupt signal line. Both 1e and 1f are signal lines on the system bus 1 and are connected to all the bus slave modules 2 requiring interrupt service and the bus master 3.

FIG. 2 shows internal blocks of the bus slave 2 and the bus master 3. The interrupt service request generated in the bus slave (1) is the interrupt factor (1)
By making the signal line 5 significant, the interrupt signal line drive circuit 9 causes the interrupt signal synchronized with the interrupt transmission timing signal 1f connected via the line receiver 10 at a predetermined timing via the line driver 11. Output to the shared interrupt signal line 1e.

Since a plurality of drivers drive one interrupt signal line, the line driver 11 uses an open collector or a line driver having a function equivalent thereto.

In the bus master 3, the shared interrupt signal line 1e passes through the line receiver 12 and the demodulation circuit 14
Entered in. The pull-up resistor 13 is for stabilizing the potential of the signal line when no bus slave is driving the interrupt signal line. The interrupt transmission timing generation circuit 15 has a specific signal pattern that allows the demodulation circuit 14 to identify an interrupt signal used in time division multiplex by an interrupt service request source, and further, an interrupt signal line on the bus slave 2. The drive circuit 9 itself generates a specific signal pattern that can determine the available time of the shared interrupt signal line.

FIG. 3 shows an example of the interrupt signal line drive circuit. The interrupt transmission timing signal 16 via the line receiver 10 is input to the one-shot multivibrator 17 and the counter 18. Counter 18 has its CLK
At the rising edge of the input, its output 0, 1, 2, 3,
~, N operates so as to become significant in order, and the RST
The input is significant and at the rising edge of its CLK input, the output 0 is reset to be significant. The one-shot multivibrator 17 operates so that its output 19 becomes significant for a certain period from the rising edge of its input signal. Counter 18
The operation timing of the one-shot multivibrator 17 is shown in FIG. As shown in FIG. 5, the interrupt transmission timing signal 16 via the line receiver 10 is a signal having a short period 20 from the rising edge to the next rising edge and a long period 21 (the same applies to the rising edge). By using and setting the period during which the output 19 of the one-shot multivibrator 17 is significantly connected in the middle of the period 20 and the period 21, the counter 18 is reset in the period 20 and the counter 18 is reset in the period 21. Counting can be performed in synchronization with the interrupt transmission timing signal. That is, the counters 18 in all the bus slave modules 2 on the system bus can all show the same count value. Therefore, an independent number is assigned to each bus slave module 2, and that number and counter 1
If the interrupt signal line can be driven when the count values of 8 match, one interrupt signal line can be shared and used by all the bus slave modules. In FIG. 3, when the count value of the counter 18 is "1", the signal line 22 is significant, and if the interrupt factor (1) of 5 is significant, it is 2
The output 24 of the AND gate of 3 becomes significant, and the shared interrupt signal line 1e is driven via the line driver 11.

FIG. 4 shows an example of the demodulation circuit 14 of the bus master 3. The method of determining which bus slave module can currently use the shared interrupt signal line 1e from the interrupt transmission timing signal 1f is the same as that of the interrupt signal line drive circuit. There are two differences from the interrupt signal line drive circuit. One is that the inverter 25 causes the demodulation circuit 14 to sample after the interrupt signal transmitted at the rising edge of the interrupt transmission timing signal becomes stable. , The interrupt signal drive timing and sampling timing are shown in 2 of FIG.
It shifts like 6. Second, since the shared interrupt signal line 1e indicates the interrupt request state of one bus slave module only for a certain period, the D flip-flop 27 is used to store the state. In FIG. 5, during the period of 28, the bus slave module (1) outputs an interrupt request to the shared interrupt signal line 1e, and the request output is a signal 21 via the line receiver 12. It is input to the D flip-flop 27. Interrupt transmission timing signal 1
f is input to the inverter 25 via the signal line 20 in the bus master 3, and at the falling edge thereof, D-
The state of the interrupt signal line in the period 28 is stored in the flip-flop 27 as indicated by 26. In the case of FIG. 4, the signal line 29 corresponds to the bus slave module (1).

The signal line group 30 including the signal line 29 is output to the interrupt control circuit 8. This signal line group 30
Has the same effect as the signal group 31 in FIG.

Embodiment 2. Next, a signal having a constant cycle is used as an interrupt transmission timing signal, and an interrupt signal line drive circuit in which an interrupt processing program on the bus master side and an interrupt mask register on the bus slave side are added in place of the demodulation circuit is the same as the first embodiment. An embodiment for obtaining the effect of will be described.

FIG. 6 is a block diagram of this embodiment. Instead of the interrupt transmission timing signal generation circuit, the bus clock generation circuit 32 outputs a clock signal 33 of a constant cycle, and the line driver 34 drives the bus clock signal line 1g. Others are the same as the configuration of the bus master in FIG. The shared interrupt signal line 1e is input to the interrupt control circuit 8 via the line receiver 12, and an interrupt is generated at the rising edge of the signal.

The interrupt signal line drive circuit 35 of the bus slave module 2 outputs the bus clock signal 1g only when the interrupt inhibit output 37 of the interrupt mask register 36 is not significant and the interrupt factor (1) of 5 is significant. The output 24 becomes significant at the rising edge, and the interrupt signal line 1e shared via the line driver 11 is set to 1
It is driven to logic "0" during the bus clock period. The shared interrupt signal line 1e is input to the line receiver 38, and its output 39 is input to the interrupt mask register 36. If the shared interrupt signal line 1e is driven by another bus slave module at least once, the output 37 of the interrupt mask register 36 becomes significant, and the interrupt mask register 36 outputs the interrupt signal line 1e shared by the own bus slave module. This is to prevent driving at an incorrect timing so that a multiple interrupt state does not occur. The bus slave module 2 needs to be able to confirm the presence / absence of the interrupt factors 5 and the state of the interrupt mask register by the bus master 3 and to be able to reset the interrupt mask register 36.

FIG. 7 shows an example of the interrupt signal line drive circuit 35 and the interrupt mask register 36. An interrupt signal for one cycle of the bus clock signal 16 can be generated by the D-flip-flops 40 and 41, and the generation condition is that 5 interrupt factors are significant and 3
7 is that the reset signal 43 of the D-flip-flops 40 and 41 is released by the AND gate 42 when the interrupt mask signal of 7 is not significant. The interrupt mask register 36 is also composed of D-flip-flops, and "H" → "L" of the shared interrupt signal line 1e.
At the falling edge of, the interrupt inhibit signal 37 becomes significant. Further, the interrupt mask register 36 is used for the bus master 3 decoded by the own bus slave module.
It can be reset by the interrupt mask register signal 44 from. The NOR gate 45 prevents the interrupt mask register from being set when the own bus slave module drives the shared interrupt signal line 1e.

FIG. 8 is a flowchart of the interrupt processing program 50 of the bus master 3. The interrupt processing program 50 is a program that is activated when an interrupt service request is transmitted from the interrupt control circuit 8 to the CPU. When activated, the interrupt request presence / absence of all bus slave modules in S1 and Check the status of the interrupt mask register. Then, in S2, the interrupt service is provided to the bus slave module having the interrupt request. Furthermore, in S3, the interrupt disable signal 3
For the bus slave module in which 7 is significant, the interrupt mask register reset signal 44 is significant,
The interrupt mask register 36 is reset.

Embodiment 3. In the above embodiment, the bus master 3
The bus slave module 2 and the bus slave module 2 are physically separated from each other via the system bus 1. However, they may exist on the same wiring board, and a physical mounting mode of the bus master 3 and the bus slave module 2 is possible. There is no particular need to pay particular attention to the above, and the same effect as that of the above embodiment can be obtained.

Example 4. In the above embodiment, the case where the interrupt signal line is shared has been described, but the case where other signal lines are shared may be used.

[0024]

As described above, according to the first and second aspects of the present invention, since a large number of required signal lines are constituted by one shared signal line, the signal lines of the entire system bus are provided. The number can be reduced, and in the function expansion of the entire system in the future, there is an effect that the function expansion limitation caused by the number of signal lines of the interrupt signal lines that can be used can be avoided.

Since this system is an extension of the conventional system and has a function to be added, the purpose of use,
The above-described effect can be obtained by changing the signal specifications slightly according to the application without changing the physical specifications of the existing system bus.

[Brief description of drawings]

FIG. 1 is a system diagram using an interrupt signal line sharing method showing an embodiment of the present invention.

FIG. 2 is an internal block diagram of a bus master and a bus slave showing an embodiment of the present invention.

FIG. 3 is a diagram of an interrupt signal line drive circuit showing an embodiment of the present invention.

FIG. 4 is a diagram of a demodulation circuit showing an embodiment of the present invention.

FIG. 5 is an operation timing chart showing an embodiment of the present invention.

FIG. 6 is an internal block diagram of a bus master and a bus slave showing an embodiment of the present invention.

FIG. 7 is a diagram of an interrupt signal line drive circuit and an interrupt mask register circuit showing an embodiment of the present invention.

FIG. 8 is a flowchart of an interrupt processing program showing an embodiment of the present invention.

FIG. 9 is a system diagram of a conventional microcomputer system.

FIG. 10 is an internal block diagram of a bus master and a bus slave of a conventional microcomputer system.

[Explanation of symbols]

 1 system bus 1e shared interrupt signal line 1f interrupt transmission timing signal line 2 bus master 3 bus slave

Claims (2)

[Claims] 1. A signal line sharing method for sharing a signal line between a master processing unit and at least one slave processing unit having the following elements: (a) Timing of connecting a master processing unit and a slave processing unit Signal line, (b) shared signal line connecting the master processing unit and the slave processing unit, (c) master processing unit having the following elements, (c1) timing at which the slave processing unit may drive the shared signal line Timing signal generating means for outputting a timing signal indicating to the timing signal line, (c2) receiving the drive signal of the shared signal line driven by the slave processing unit and specifying from which slave processing unit the drive signal is sent. Receiving means, (d) based on the timing signal from the master processing unit,
A slave processing unit having a driving unit that outputs a driving signal to the shared signal line. 2. A signal line sharing method for sharing a signal line between a master processing unit and one or more slave processing units, comprising: (a) a clock signal connecting the master processing unit and the slave processing unit; A line, (b) a shared signal line connecting the master processing unit and the slave processing unit, (c) a master processing unit having the following elements, (c1) clock generation means for outputting a clock signal to the clock signal line, (c2) ) A processing unit which is activated by a drive signal of a shared signal line driven by a slave processing unit and identifies which slave processing unit the drive signal is from, (d) a slave processing unit having the following elements, (d1) Based on the clock signal from the master processor,
Drive means for outputting a drive signal to the shared signal line, and (d2) prohibition means for detecting the drive of the shared signal line by the signal drive means of the other slave processing unit and for inhibiting execution of its own signal drive means.