JPH11353272A - Information transfer method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information transfer device which can reduce its circuit scale by simplifying the hardware constitution of a bus arbitration means. SOLUTION: The request circuits 400 and 4n0 of input/output means 40 and 4n periodically transmit the bus use request signals to a bus use request line 6 in the timing synchronous with the frame signal that is sent from a system clock distribution means 2. The bus use request signals are added together via both circuits 400 and 4n0 and the bus use request signal having the largest number of pulses is received by a bus arbitration means 3. The means 3 transmits and receives the bus use request 9 and bus use permission 10 to and from a processor 1 and returns the bus use request signals to the permission circuits 401 and 4n1 of the means 40 and 4n as the bus use enabling signals. The number of pulses of the bus use enabling signal is compared with that of the transmitted bus use request signal. When both numbers of pulses are coincident with each other, the means 40 and 4n acquire the use right of a bus 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information transfer method and an information transfer apparatus connected with a plurality of input / output means for transferring data to a bus connecting a processor and a memory, and a system clock distribution means.

[0002]

2. Description of the Related Art Conventionally, as this type of information transfer apparatus,
For example, a configuration described in Japanese Patent Application Laid-Open No. 9-198342 is known.

In the information transfer apparatus described in Japanese Patent Application Laid-Open No. HEI 9-198342, a plurality of input / output means and a bus arbitration means are used to convert a bus use request and a priority order from each input device into a predetermined time slot. The connection is made via a request highway that is inserted and transferred to the bus adjustment means. Further, each input / output device and the bus arbitration unit are connected by a permission highway for transferring a bus use permission to each input / output device. The bus arbitration means receives a bus use request and a priority order from the plurality of input devices, and after receiving the use request, makes a bus use request to the processor and receives a bus use permission from the processor. Outputting a bus use permission to each input / output device according to the priority received from the output device, and preventing a bus use request and a use permission signal of the bus connected to the bus arbitration device from increasing with the number of input / output devices; The priority of the bus can be changed so that an input / output device with a lower priority can use the bus.

[0004]

However, in the conventional information transfer apparatus described in Japanese Patent Application Laid-Open No. HEI 9-198342, the number of bus use request and use permission signals is reduced, but the reception of the bus arbitration means is not possible. Hardware such as a control unit and a transmission control unit becomes complicated, and as a result, the circuit scale may be increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide an information transfer method and an apparatus for simplifying a hardware configuration of a bus arbitration unit and reducing a circuit scale.

[0006]

According to the present invention, there is provided an information transfer method comprising: a bus connecting a processor and a memory; a plurality of input / output means connected to the bus for transferring information to the memory; a clock and a frame. And a bus arbitration unit for selecting any one of the plurality of input / output units and transferring information to the memory via the bus by the selected input / output unit. In the information transfer method in the information transfer apparatus, the plurality of input / output units transmit bus use request signals having different numbers of pulses to the bus arbitration unit in synchronization with a frame signal from a system clock distribution unit.

[0007] The information transfer method according to the second aspect is the first aspect.
In the information transfer method described above, a bus use request signal sent from a plurality of input / output means is output as a bus use permission signal by the bus arbitration means, and the returned bus use permission signal is transmitted from the system clock distribution means. The information is transferred to the memory via the bus by any one of the input / output means determined to be equal to the number of pulses of the bus use request signal transmitted in synchronization with the frame signal.

According to a third aspect of the present invention, there is provided an information transfer method.
In the described information transfer method, the plurality of input / output means stops outputting the bus use request signal when the counted number of pulses of the bus use permission signal is different from the output bus use request signal.

[0009] The information transfer method according to the fourth aspect is the first aspect.
In the information transfer method according to any one of Items 1 to 3,
A bus use request signal is added from a plurality of input / output means and sent to the bus arbitration means.

According to a fifth aspect of the present invention, there is provided an information transfer apparatus, comprising: a bus for connecting a processor and a memory; a system clock distribution means for distributing a clock and a frame; and a frame signal from the system clock distribution means connected to the bus. A plurality of input / output means for outputting bus use request signals having different numbers of pulses in synchronization with each other; and a predetermined bus use permission signal connected to the processor based on the bus use request signals from the plurality of input / output means. A bus arbitration unit that outputs a signal to the plurality of input / output units to select a specific input / output unit, and transfers information to the memory via the bus by the selected input / output unit. is there.

[0011] The information transfer device according to the sixth aspect is the fifth aspect of the invention.
In the information transfer device described in the above, the bus arbitration means returns a bus use request signal from a plurality of input / output means as a bus use permission signal, and said plurality of input / output means outputs a bus use request signal having a different number of pulses. And the number of pulses of the bus use permission signal looped back from the bus arbitration means is counted, and when the same bus use permission signal as the output bus use request signal is recognized, the signal is transmitted through the bus. To transfer information to the memory.

[0012] According to a seventh aspect of the present invention, there is provided an information transfer apparatus.
In the information transfer device described above, the plurality of input / output units stop outputting the bus use request signal when the counted number of pulses of the bus use permission signal is different from the output bus use request signal.

[0013] The information transfer device according to the eighth aspect is the fifth aspect.
7. The information transfer device according to any one of items 1 to 7,
A plurality of input / output means are connected in series, and a bus use request line for adding a bus use request signal from each input / output means and transferring the signal to a bus arbitration means is provided.

According to a ninth aspect of the present invention, there is provided an information transfer apparatus according to the fifth aspect.
9. The information transfer device according to any one of items 1 to 8,
A plurality of input / output means are connected in series, and the plurality of input / output means are provided with a bus use permission line for transmitting a return bus use permission signal from the bus arbitration means.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a configuration of an information transfer apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an information transfer apparatus according to an embodiment of the present invention.

The information transfer device shown in FIG.
have. The processor 1 has a memory 5
Is connected, and the processor 1 is connected to the bus 8.
The memory 5 is accessed via. Also, a plurality of input / output units 40 and 4n are connected to the bus 8, and the input / output units 40 and 4n access the memory 5 via the bus 8 and transfer data to the memory 5. These input / output means 40 and 4n include request circuits 400 and 4n0 and permission circuits 401 and 4n1, respectively. Also,
The input / output means 40 and 4n are connected to the bus use request line 6, respectively, and the request circuits 400 and 4n0 are connected in series.

The system clock distribution means 2 is connected to the bus use request line 6. The system clock distribution means 2 outputs a clock signal and a frame signal to distribute a clock and a frame. Then, each of the input / output means 40 and 4n sends out a pulse-like bus use request signal synchronized with the frame signal received from the system clock distribution means 2 to the bus use request line 6. That is, the request circuits 400, 4n of the input / output means 40, 4n
0 sends out a number of pulses equal to a value preset and assigned to each input / output means 40, 4n. The bus use request signal is a different number of pulse signals for each of the input / output means 40 and 4n. The input / output means 4n uses one pulse and the input / output means 40 uses n + 1 pulse signals as bus use request signals. The transmitted bus use request signal is added while passing through the input / output means 40 and 4n.

Further, the bus arbitration means 3 is connected to the bus use request line 6. And the bus arbitration means 3
When one pulse of the bus use request signal received from the input / output means 40, 4n via the bus use request line 6 is recognized, the pulse signal is converted into a level to send the bus use request 9 to the processor 1, and The bus use permission 10 returned from 1 is received. Further, a bus use permission line 7 is connected to the bus arbitration means 3. When the bus arbitration unit 3 returns the bus use permission 10 from the processor 1, the bus arbitration unit 3 sends the bus use request signal received from the input / output units 40 and 4n via the bus use request line 6 to the input / output unit 4
The signal is returned to the bus 0, 4n via the bus use permission line 7 as a bus use permission signal.

Each of the input / output means 40 and 4n counts the pulse of the bus use permission signal received from the bus arbitration means 3 via the bus use permission line 7 in each of the permission circuits 401 and 4n1, and outputs the bus signal to itself. It is determined whether the signal is a use permission signal. Each of the permission circuits 401 and 4n1 recognizes that the number of pulses of the bus use permission signal transmitted from the request circuits 400 and 4n0 matches the number of pulses of the bus use permission signal, and that the input / output means 40 and 4n have the input / output means 40 and 4n. Acquire the right to use the bus. Also, each of the permission circuits 401 and 4n1
If it recognizes that the signal is not the bus use permission signal for itself, it outputs a signal to the corresponding request circuits 400 and 4n0 to stop sending the bus use request signal.

Next, the operation of the information transfer method of the information transfer apparatus according to the embodiment will be described with reference to FIG.

FIG. 2 is a timing chart for explaining the operation of the information transfer apparatus.

First, the system clock distribution means 2 outputs a frame signal and a clock signal to the bus arbitration means 3 and the input / output means 40 and 4n to distribute the frame and the clock.

Each of the request circuits 400 and 4n0 of each of the input / output means 40 and 4n periodically sends a bus use request signal to the bus use request line 6 at a timing synchronized with the frame signal. The transmitted bus use request signal is transmitted to the request circuits 400, 4n of the input / output means 40, 4n connected in series.
The bus arbitration means 3 receives the bus use request signal having the largest number of pulses as the bus use request signal.

That is, for example, when the input / output means 4n periodically outputs the bus use request signal as one pulse to the bus use request line 6, the signal is input to the request circuit 400 of the input / output means 40. At this time, at the same time, the input / output means 40 periodically outputs the bus use request signal synchronized with the frame signal received from the system clock distribution means 2 to the bus use request line 6 as n + 1 pulses.

Thereafter, the bus arbitration means 3 transmits a bus use request 9 to the processor 1 by receiving one or more pulses of a pulse-like bus use request signal. That is, the bus arbitration unit 3 periodically receives the (n + 1) pulse signals as the bus use request signal, and receives one of the received pulses.
When the number is detected, it is converted to a level and a bus use request 9 is transmitted.

The bus arbitration means 3 is provided with the processor 1
Receive the bus use permission 10 from the input / output means 40, 4n
Input / output means 40, 4n
Is sent back to the bus use permission line 7 as a bus use permission signal.

Further, the permission circuits 401 and 4n1 of the input / output means 40 and 4n count the number of pulses of the bus use permission signal received via the bus use permission line 7, and determine the number of pulses of the bus use request signal transmitted. Compare. Then, as a result of the comparison, the input / output means 40 which determines that the number of pulses is equal,
4n acquires the right to use the bus 8. That is, the permission circuit 401 acquires the right to use the bus by recognizing the pulse n + 1 of the bus use permission signal.

As a result of the comparison, if it is determined that the number of pulses is not equal, a signal to stop the bus use request signal is output to the request circuits 400 and 4n0. That is, the permission circuit 4n1 determines that the number of pulses is not 1 but n +
Since it is 1, a signal to stop the bus use request signal is output to the request circuit 4n0.

When the use of the bus 8 of the input / output means 40 is completed, the output of the bus use request signal from the request circuit 400 is stopped, and the bus arbitration means 3 sets the processor 1
The bus 8 is released at the same time, the bus use permission signal is stopped at the same time, and all the buses 8 are released.

As described above, in the above embodiment, the bus use request line 6 and the bus use permission line 7 are provided one by one, and the circuit configuration of the bus arbitration means 3 is such that the received bus use request signal is The signal can be simply returned and transmitted as it is, and the logic of the arbitration circuit of the bus arbitration means 3 can be simplified, so that the circuit scale can be reduced.

[0032]

According to the present invention, a plurality of input / output means for transferring information to a memory via a bus arbitrate bus use request signals having different numbers of pulses in synchronization with a frame signal from a system clock distribution means. Means for transmitting a bus use request signal to the bus arbitration means in correspondence with the plurality of input / output means.
A single wiring is possible, and the circuit scale can be reduced.

Further, the bus use request signal is looped back and output by the bus arbitration means as a bus use permission signal, and the returned bus use permission signal is output in synchronization with the frame signal from the system clock distribution means. When any of the plurality of input / output means determines that the number of pulses is equal to the number of pulses of the request signal, the input / output means transfers information to the memory via the bus. Since the bus use request signal is transmitted as it is without analyzing the bus use request signal, the hardware scale of the bus arbitration means can be simplified.

Further, when the number of pulses of the bus use permission signal is different from the output bus use request signal, the output of the bus use request signal is stopped, so that unnecessary signals are cut off and information can be transferred without malfunction.

The bus use request signals are added from the plurality of input / output means and sent to the bus arbitration means, and the bus use request signal having the largest number of pulses is recognized by the bus arbitration means. A bus use request signal can be sent from the output means to the bus arbitration means.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information transfer device according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating an operation of the information transfer apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processor 2 System clock distribution means 3 Bus arbitration means 5 Memory 6 Bus use request line 7 Bus use permission line 8 Bus 9 Bus use request 10 Bus use permission 40,4n Input / output means 400,4n0 Request circuit 401,4n1 Permit circuit

Claims (9)

[Claims] A bus connecting the processor and the memory; a plurality of input / output means connected to the bus for transferring information to the memory; a system clock distribution means for distributing a clock and a frame; A bus arbitration means for selecting one of the means and transferring the information to the memory via the bus by the selected input / output means. The information transfer method, wherein the means sends a bus use request signal having a different number of pulses to the bus arbitration means in synchronization with a frame signal from a system clock distribution means. 2. A bus use request signal sent from a plurality of input / output means is returned and output as a bus use permission signal by a bus arbitration means, and the returned bus use permission signal is output from a frame from a system clock distribution means. 2. The information transfer according to claim 1, wherein the information is transferred to the memory via the bus by any one of the input / output means determined to be equal to the pulse number of the bus use request signal transmitted in synchronization with the signal. Method. 3. The system according to claim 2, wherein the plurality of input / output means stops outputting the bus use request signal when the counted number of pulses of the bus use permission signal is different from the output bus use request signal. Information transfer method. 4. The information transfer method according to claim 1, wherein a bus use request signal is added from a plurality of input / output means and sent to a bus arbitration means. 5. A bus for connecting a processor and a memory; a system clock distributing means for distributing a clock and a frame; and a bus connected to the bus and having different numbers of pulses in synchronization with a frame signal from the system clock distributing means. A plurality of input / output means for outputting a bus use request signal; a plurality of input / output means connected to the processor, for outputting a predetermined bus use permission signal to the plurality of input / output means based on the bus use request signals from the plurality of input / output means A bus arbitration means for selecting a specific input / output means and transferring the information to the memory via the bus by the selected input / output means. 6. A bus arbitration means for returning a bus use request signal from a plurality of input / output means as a bus use permission signal, and said plurality of input / output means outputting a bus use request signal having a different number of pulses, respectively. And counting the number of pulses of the bus use permission signal looped back from the bus arbitration means, and recognizing the same bus use permission signal as the outputted bus use request signal, via the bus. The information transfer device according to claim 5, wherein the information is transferred to a memory. 7. The system according to claim 7, wherein the plurality of input / output units stop outputting the bus use request signal when the counted number of pulses of the bus use permission signal is different from the output bus use request signal. 6. The information transfer device according to item 6. 8. A bus use request line for connecting a plurality of input / output means in series, adding a bus use request signal from each input / output means and transferring the signal to a bus arbitration means. Item 8. The information transfer device according to any one of Items 5 to 7. 9. A plurality of input / output means are connected in series, and the plurality of input / output means are provided with a bus use permission line for sending a return bus use permission signal from the bus arbitration means. 9. The information transfer device according to any one of 5 to 8.