JP3487761B2 - Information transfer device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information transfer system in which a plurality of input / output means for transferring data to a bus connecting a processor and a memory and a system clock distribution means are connected.
Regarding the sending device .

[0002]

2. Description of the Related Art Conventionally, as this type of information transfer device,
For example, the structure described in Japanese Patent Laid-Open No. 9-198342 is known.

In the information transfer device described in Japanese Patent Laid-Open No. 9-198342, a plurality of input / output means and a bus arbitration means are used, and a bus use request from each input device and a priority order are assigned to predetermined time slots. Connected by the request highway which is inserted and transferred to the bus adjusting means. Further, each input / output device and the bus arbitration means are connected by a permission highway for transferring permission of use of the bus to each input / output device. The bus arbitration means receives a bus use request and priority from a plurality of input devices, issues a bus use request to the processor after receiving the use request, and receives a bus use permission from the processor. The bus permission is output to each input / output device according to the priority received from the output device, and the use request and use permission signals of the bus connected to the bus arbitration device are prevented from increasing with the number of input / output devices. The priority of a bus can be changed so that an I / O device having a lower priority can use the bus.

[0004]

However, in the conventional information transfer apparatus described in Japanese Patent Laid-Open No. 9-198342, the number of bus use request and use permission signals decreases, but the reception of the bus arbitration means. The hardware such as the control unit and the transmission control unit may be complicated, resulting in a large circuit scale.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an information transfer device which simplifies the hardware configuration of the bus arbitration means and reduces the circuit scale.

[0006]

The present invention according to claim 1 of the present invention is directed to a processor which is connected to a bus (8) to which a memory (5) is connected and which accesses the memory via the bus. (1) and a plurality of first request circuits (400), ..., N + 1th request circuit (4n0) and first permission circuits (401), ..., N + 1th permission circuit (4n1), respectively. A plurality of first input / output means (40), ..., N + 1th input / output means (4n) for accessing the memory via the bus and transferring data to the memory, and the first request circuit , ..., the n + th
A bus request line connecting each of the first request circuit in series form (6), said first permission circuit (401), ..., a
A bus use permission line (7) that connects each of the n + 1 permission circuits (4n1) in series, and a system clock that is connected to the bus use request line and outputs a clock signal and a frame signal to distribute the clock and the frame. The distribution means (2) is connected to the bus use request line and the bus use permission line, and is connected to the first input / output means, ..., And the n + th.
The bus use request signal received from the I / O unit 1 via the bus use request line is recognized, the bus use request (9) is sent to the processor, and the bus use permission (10) is returned from the processor. And the bus arbitration means (3) for transmitting the bus use permission to the bus use permission line, the first input / output means, ..., The nth
The +1 input / output unit outputs the pulsed bus use request signal synchronized with the frame signal received from the system clock distribution unit to the bus use request line when transmitting the pulsed bus use request signal to the bus use request line.
, The n + 1th request circuit sends out a number of pulses equal to a value preset and assigned to the first input / output unit, ..., The n + 1th input / output unit, and At this time, the first input / output means, ..., The first
As a different number of pulses for each of the n + 1 input / output means, the n + 1th input / output means sends one pulse and the first input / output means sends the n + 1 pulse as the bus use request signal, and the bus use request is issued. The signal is the first input / output means,
..., addition is performed while passing through the (n + 1 ) th input / output unit, and the bus arbitration unit is added to the first input / output unit ,.
When one pulse of the bus use request signal received from the (n + 1 ) th input / output unit via the bus use request line is recognized, the pulse is converted into a level and the bus use request is sent to the processor. When the bus use permission returned from the processor is received, and when the bus use permission is returned from the processor, the bus use is performed from the first input / output unit, ..., The n + 1th input / output unit. The bus use request signal received via the request line is sent back to the first input / output unit, ..., And the n + 1th input / output unit as the bus use permission signal via the bus use permission line. The first input / output means,
..., the (n + 1 ) th input / output unit receives the bus use permission signal received from the bus arbitration unit via the bus use permission line in each of the first permission circuit ,. The number of pulses is counted, it is determined whether or not it is a bus use permission signal for itself, the first permission circuit,
..., each of the n + 1th permission circuits is a bus use permission signal for itself that matches the number of pulses of the bus use request signal transmitted from the first request circuit, ..., The n + 1th request circuit. by recognizing the first input and output unit, ..., the (n + 1) th output means obtains the right to use the bus, the first permission circuit, ..., the (n + 1) -th
When each of the permission circuits recognizes that it is not a bus use permission signal for itself, the effect that the transmission of the bus use request signal to the corresponding first request circuit, ..., And the n + 1th request circuit is stopped. The information transfer device is characterized by outputting the signal of. Further, the gist of the invention according to claim 2 of the present invention is that the system clock distribution means comprises the bus arbitration means and the first input / output means,
..., the frame signal and the clock signal are output to the (n + 1 ) th input / output unit to distribute the frame and the clock, and the first input / output unit is provided in the (n + 1 ) th input / output unit. The first request circuit (40
0), ..., Each of the (n + 1 ) th request circuits periodically sends a bus use request signal to the bus use request line at a timing synchronized with a frame signal, and the sent bus use request signal is serially transmitted. , The first request circuit and the (n + 1) th request circuit provided in the (n + 1 ) th input / output means, and the bus arbitration means performs addition. At this time, the bus use request signal having the largest number of pulses is received as the bus use request signal, and at this time, the n + 1th input / output means periodically sends the bus use request signal as one pulse to the bus use request line. To the first input / output means of the first input / output means,
Of the bus use request signal simultaneously input to the request circuit of the first input / output unit and synchronized with the frame signal received from the system clock distribution unit, is periodically output to the bus use request line as n + 1 pulses. After that, the bus arbitration means receives n + 1 pulses as a bus use request signal when transmitting the bus use request to the processor by receiving one or more pulsed bus use request signals. When the first pulse of the received pulse is detected periodically, it is converted into a level and the bus use request is transmitted, and further, the bus use permission is received from the processor, and the first input / output unit, ..., the n + th
The bus use request signal received from each of the first input / output means is sent back to the bus use permission line as a bus use permission signal to each of the first input / output means, ..., And the n + 1th input / output means. , The first permission circuit,
..., the n + 1th permission circuit counts the number of pulses of the bus use permission signal received via the bus use permission line, compares it with the number of pulses of the bus use request signal sent out, and as a result of the comparison, the number of pulses 2. The first input / output means, ..., And the (n + 1 ) th input / output means, which have been determined to have equality, acquire the right to use the bus.
The information transfer device described in 1. exists.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Next, the configuration of an information transfer apparatus showing an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an information transfer apparatus showing an embodiment of the present invention.

The information transfer apparatus shown in FIG. 1 includes a processor 1
have. The processor 1 has a memory 5
Is connected to the bus 8 and the processor 1 is connected to the bus 8
The memory 5 is accessed via. A plurality of input / output means 40, 4n are connected to the bus 8, and these input / output means 40, 4n access the memory 5 via the bus 8 and transfer data to the memory 5. The input / output units 40 and 4n include request circuits 400 and 4n0 and permission circuits 401 and 4n1, respectively. Also,
The input / output units 40 and 4n are connected to the bus use request line 6, and the request circuits 400 and 4n0 are connected in series.

The system clock distribution means 2 is connected to the bus use request line 6. The system clock distribution means 2 outputs a clock signal and a frame signal to distribute the clock and the frame. Then, each of the input / output means 40, 4n sends a pulsed bus use request signal synchronized with the frame signal received from the system clock distribution means 2 to the bus use request line 6. That is, the request circuits 400, 4n of the input / output means 40, 4n.
0 outputs a number of pulses equal to the value preset and assigned to each input / output unit 40, 4n. The bus use request signal is a different number of pulse signals for each of the input / output units 40 and 4n. The input / output unit 4n has one pulse and the input / output unit 40 has n + 1 pulse signals as the bus use request signal. The bus use request signals sent out are added while passing through the input / output means 40, 4n.

Further, a bus arbitration means 3 is connected to the bus use request line 6. And the bus arbitration means 3
When one pulse of the bus use request signal received from the input / output means 40, 4n via the bus use request line 6 is recognized, the pulse signal is converted into a level and the bus use request 9 is sent to the processor 1 and at the same time, the processor The bus use permission 10 returned from 1 is received. Further, a bus use permission line 7 is connected to the bus arbitration means 3. Then, the bus arbitration means 3 receives the bus use request signal from the input / output means 40 and 4n via the bus use request line 6 when the bus use permission 10 is returned from the processor 1, and the input / output means 4 receives the bus use request signal.
The signal is sent back to 0 and 4n via the bus use permission line 7 as a bus use permission signal.

Further, each of the input / output means 40, 4n counts the pulses of the bus use permission signal received from the bus arbitration means 3 via the bus use permission line 7 in each permission circuit 401, 4n1 so as to count the bus for itself. It is determined whether the signal is a use permission signal. Then, each of the permission circuits 401 and 4n1 agrees with the number of pulses of the bus use request signal sent from the request circuits 400 and 4n0, and recognizes that the bus use permission signal is for itself, so that the input / output unit 40, 4n Acquire the right to use the bus. Each permission circuit 401,4n1 is, when recognized as not bus grant signal to the self outputs a signal for stopping the sending of the bus use request signal to the corresponding request circuit 400,4N0.

Next, the operation of the information transfer system of the information transfer apparatus of the above embodiment will be described with reference to FIG.

FIG. 2 is a timing chart for explaining the operation of the above information transfer device.

First, the system clock distribution means 2 outputs a frame signal and a clock signal to the bus arbitration means 3 and the input / output means 40, 4n to distribute the frame and the clock.

Then, the request circuits 400 and 4n0 of the input / output means 40 and 4n periodically send the bus use request signal to the bus use request line 6 at the timing synchronized with the frame signal. The transmitted bus use request signal is sent to the request circuit 400 of each input / output unit 40, 4n connected in series.
It is added while via 4N0, Ru received the largest number bus use request signal of the pulse number by bus arbitration unit 3 as a bus use request signal.

That is, for example, when the input / output unit 4n periodically outputs the bus use request signal as one pulse to the bus use request line 6, it is input to the request circuit 400 of the input / output unit 40. This time is output at the same time output means 40 periodically to the system clock distribution unit bus request line 6 bus use request signal synchronized with the frame signal received by the n + 1 pulses from 2.

After that, the bus arbitration means 3 transmits the bus use request 9 to the processor 1 by receiving one pulse or more of the pulsed bus use request signal. That is, the bus arbitration means 3 periodically receives n + 1 pulse signals as a bus use request signal, and receives 1 of the received pulses.
When the number is detected, it is converted into a level and the bus use request 9 is transmitted.

The bus arbitration means 3 is the processor 1
The bus use permission 10 is received from the input / output means 40, 4n.
The bus use request signal received from the input / output means 40, 4n
To the bus use permission line 7 as a bus use permission signal.

Further, the permission circuits 401, 4n1 of the input / output means 40, 4n count the number of pulses of the bus use permission signal received via the bus use permission line 7 and determine the number of pulses of the transmitted bus use request signal. Compare. Then, as a result of the comparison, the input / output unit 40, which determines that the number of pulses is equal,
4n acquires the right to use the bus 8. That is, the permission circuit 401 acquires the bus use right by recognizing the pulse n + 1 of the bus use permission signal.

When it is determined that the numbers of pulses are not equal as a result of the comparison, a signal for stopping the bus use request signal is output to the request circuits 400 and 4n0. That is, the permitting circuit 4n1 has n + pulse number instead of 1.
Since it is 1, a signal for stopping the bus use request signal is output to the request circuit 4n0.

When the use of the bus 8 of the input / output means 40 is completed, the output of the bus use request signal from the request circuit 400 is stopped, and the bus arbitration means 3 causes the processor 1 to operate.
The bus 8 is released, the bus use permission signal is also stopped at the same time, and the entire bus 8 is released.

As described above, in the above embodiment, the bus use request line 6 and the bus use permission line 7 are provided one by one, and the received bus use request signal is used as the circuit configuration of the bus arbitration means 3. As a result, the simplification of sending back as it is can be realized , and the circuit scale can be reduced by simplifying the logic of the arbitration circuit of the bus arbitration means 3.

[0024]

According to the present invention, a plurality of input / output means for transferring information to a memory via a bus synchronizes with a frame signal from a system clock distributing means to arbitrate bus use request signals having different pulse numbers. Since it is sent to the means, it is not necessary to provide a wire for sending the bus use request signal to the bus arbitration means corresponding to the plurality of input / output means.
Even one wiring is possible, and the circuit scale can be reduced.

Further, the bus use request signal is returned by the bus arbitration means as a bus use enable signal, and the bus use enable signal output by return is sent in synchronization with the frame signal from the system clock distributing means. When any of the plurality of input / output means determines that the number of pulses of the request signal is equal, the bus arbitration means transfers the information to the memory via the bus by the input / output means. Since the bus use request signal is not analyzed but transmitted as it is as the bus use permission signal, the hardware scale of the bus arbitration means can be simplified.

Furthermore, when the number of pulses of the bus use request signal is different from the output bus use request signal, the output of the bus use request signal is stopped, so that unnecessary signals are blocked and information can be transferred without malfunction.

Since a bus use request signal is added from a plurality of input / output means and sent to the bus arbitration means, and the bus use request signal having the largest number of pulses is recognized by the bus arbitration means, a plurality of input / output terminals are provided by one wiring. A bus use request signal can be sent from the output means to the bus arbitration means.

[Brief description of drawings]

FIG. 1 is a block diagram of an information transfer device showing an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the above information transfer device.

[Explanation of symbols]

1 processor 2 System clock distribution means 3 bus arbitration means 5 memory 6 Bus use request line 7 bus use permission line 8 buses 9 Bus use request 10 bus use permission 40,4n input / output means 400, 4n0 request circuit 401, 4n1 permission circuit

Continuation of front page (56) Reference JP-A-9-198342 (JP, A) JP-A-57-25027 (JP, A) JP-A-7-73138 (JP, A) JP-A-4-291440 (JP , A) JP 63-223853 (JP, A) JP 58-37725 (JP, A) JP 50-66127 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB) Name) G06F 13/362

Claims (2)

(57) [Claims] 1. A processor (1) connected to a bus (8) to which a memory (5) is connected, and accessing the memory via the bus, and a plurality of first request circuits (400) ,. The (n + 1 ) th request circuit (4n0) and the first permission circuit (401), ...,
A plurality of first input / output units (40) each having an ( n + 1 ) th permission circuit (4n1) and accessing the memory via the bus to transfer data to the memory;
..., the (n + 1 ) th input / output unit (4n), the first request circuit, ..., The bus use request line (6) for connecting each of the n + 1th request circuits in series, and the first permission. Circuit (401), ..., n + 1th permission times
A bus use permission line (7) for connecting each of the paths (4n1) in series, and a system clock distribution unit (6) connected to the bus use request line for outputting a clock signal and a frame signal to distribute the clock and the frame ( 2) and connected to the bus use request line and the bus use permission line,
The bus use request signal received from the first input / output unit, ..., The n + 1th input / output unit via the bus use request line is recognized, and a bus use request (9) is sent to the processor. Bus arbitration means (3) for receiving the bus use permission (10) returned from the processor and transmitting the bus use permission to the bus use permission line, the first input / output means ,. The (n + 1 ) th input / output unit sends the pulsed bus use request signal in synchronization with the frame signal received from the system clock distribution unit to the bus use request line, the first request circuit, ...
The n + 1th request circuit is the first input / output unit, ...,
The number of pulses equal to the value preset and assigned to the unit of the (n + 1 ) th input / output unit is transmitted, and at this time, the number of pulses is different for each of the first input / output unit ,. and as the number of pulses, the first n + 1 of the input and output means said first input-output means in one pulse of the (n + 1)
A pulse is sent out as the bus use request signal, and the bus use request signal is sent to the first input / output means, ..., The n + th.
Are added while via one of the input and output means, said bus arbitration means, said first output means, ..., the
When one pulse of the bus use request signal received from the (n + 1 ) th input / output means via the bus use request line is recognized,
Together converts the pulses to a level sending the bus request to the processor to receive the bus grant sent back from the processor, also, when the bus grant from said processor is returned, the first input-output means, ..., a bus use request signal received via said bus request lines from the (n + 1) th output means said first input and output unit, ..., the (n + 1) th output means via said bus grant line to loopback transmitted as the bus grant signal, also the first input and output unit, ..., the (n + 1) th output means, the first permission circuit, ..., the first Each of the n + 1 permission circuits counts the pulse of the bus use permission signal received from the bus arbitration means via the bus use permission line to determine whether or not the bus use permission signal is for itself. Cross, and the first permission circuit, ..., each of the (n + 1) th permission circuit, said first request circuit, ..., the number of pulses of the bus use request signal transmitted from the n + 1 of the request circuit and one The first input / output unit, ..., The n + 1th input / output unit acquires the bus use right by recognizing the bus use permission signal for itself, and the first permission circuit ,. if each of the (n + 1) th permission circuit recognizes not the bus grant signal to the self, the corresponding first request circuit, ..., the first
An information transfer device, which outputs a signal for stopping transmission of a bus use request signal to an ( n + 1 ) request circuit. Wherein said system clock distribution means the bus arbitration means and said first input and output unit, ..., the n-th
And outputs a frame signal and a clock signal to the output means of +1 distributing frame and clock, said first input and output unit, ..., the (n + 1) th first provided in the output means Request circuit (400), ...,
Each of the (n + 1 ) th request circuits periodically sends a bus use request signal to the bus use request line at a timing synchronized with a frame signal, and the sent bus use request signal is connected in series. The first request circuit and the nth input / output means provided in the (n + 1 ) th input / output means
The bus arbitration unit receives the bus use request signal having the largest number of pulses as a bus use request signal, and the n + 1th input / output unit causes the bus use request to be added. When a signal is periodically output to the bus use request line as one pulse, it is input to the first request circuit of the first input / output unit, and at the same time, the first input / output unit is distributed by the system clock. The bus use request signal synchronized with the frame signal received from the means is periodically output to the bus use request line as n + 1 pulses, and then the bus arbitration means outputs one pulse of the pulsed bus use request signal. When the bus use request is transmitted to the processor by receiving the above, n + 1
The pulse is periodically received as a bus use request signal, and when the first pulse of the received pulse is detected, the pulse is converted into a level and the bus use request is transmitted. Further, the bus use permission is received from the processor, and First input / output means, ...
The bus use request signal received from each of the (n + 1 ) th input / output means is transferred to the first input / output means, ..., The n + th input / output means.
The first permission circuit, ..., And the (n + 1) th permission circuit sends back to each of the first input / output means as a bus use permission signal on the bus use permission line.
The number of pulses of the bus use permission signal received via the bus use permission line is counted and compared with the number of pulses of the transmitted bus use request signal, and as a result of the comparison, the first input determined to have the same number of pulses. 2. The information transfer apparatus according to claim 1, wherein each of the output means, ..., And the (n + 1 ) th input / output means acquires a right to use the bus.