JPH05108563A - High-speed bus extending method - Google Patents

Abstract

PURPOSE:To fix the delay time of a data signal from a slave device in respect of a clock signal regardless of the position of the slave device by extending an incoming path common data bus from the slave device at the most distant place, among plural slave devices, to a main device and directly connecting the data bus to the main device. CONSTITUTION:Synchronously with the clock signal, the data signal from a main device 101 is branched at coupling points S2, S3 and S4 on an outgoing path common data bus 106 behind a coupling point S1 by a bus driving circuit 109 and inputted to bus receiving circuits 112, 115 and 118 of slave devices 102, 103 and 104. The output data signals of the slave devices 102, 103 and 104 are transmitted through bus driving circuits 113, 116 and 119 to n incoming path data bus 107 at the coupling points R2, R3 and R4. The incoming path common data bus 107 is extended from the slave device 104 positioned in the most distant position from the main device 101 on the outgoing path common data bus 106 and directly connected to the main device 101 at an input point R1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed bus extension method which is used in high-speed data transfer between electronic equipment blocks constituting an electronic equipment device and is accompanied by the addition of electronic equipment blocks.

[0002]

2. Description of the Related Art FIG. 9 is a bus configuration diagram showing a high-speed bus extension method as a first conventional example. In the figure, 1, 2,
Reference numerals 3 and 4 denote electronic device blocks that make up the electronic device apparatus, 1 of which is an electronic apparatus block as a main device (hereinafter referred to as a main device), and 2, 3 and 4 are electronic devices as slave devices. It is a block (hereinafter referred to as a slave device).

Reference numerals 5, 6 and 7 denote bus transmission lines connecting the main unit 1 and the slave unit 2, the main unit 1 and the slave unit 3, and the main unit 1 and the slave unit 4, respectively, in the direction from the main unit to the slave unit. And a set of signal paths from the slave device to the master device.

The bus receiving circuits 8, 10, 12, 14, 16, 18 are mounted in the electronic device blocks 1, 2, 3 and 4, respectively, and receive data from the bus transmission lines 5, 6 and 7, respectively. , 11, 13, 15, 17, 1
Reference numeral 9 denotes a bus drive circuit which is mounted on each of the electronic device blocks 1, 2, 3 and 4 and drives the bus transmission lines 5, 6, and 7, respectively.

The operation of the above conventional example is as follows. Figure 9
In FIG. 1, the main unit 1 has a reference clock signal source (particularly not shown), and a data signal synchronized with the clock signal from the reference clock source is supplied to the bus drive circuits 9, 11 and 13 together with the clock signal. Bus transmission line 5,
The data is transmitted to the electronic device blocks 1, 2, and 3 of the slave device via 6, 7 (in FIG. 7, the master device 1 to the slave device 2,
The clock signal and the data signal are not particularly distinguished and drawn in the bus transmission paths to 3 and 4).

The slave devices 2, 3 and 4 operate using the received clock signal as a master clock, and return the data signal transmitted from the slave devices 2, 3 and 4 to the main device 1 in synchronization with the clock signal. ..

FIG. 10 is a diagram showing a data format on the bus transmission lines 5, 6, and 7. As shown in (a) of FIG. 10, the signal line from the main device to the slave device in the bus transmission lines 5, 6, and 7 is provided with the clock signal and a data signal of, for example, an 8-bit width synchronized with the clock signal. Included, while Figure 1
As shown in (b) of 0, the signal line extending from the slave device to the master device in the bus transmission lines 5, 6 and 7 similarly includes, for example, a data signal of 8-bit width synchronized with the clock signal. There is.

A bus configuration diagram showing a high-speed bus extension method as a second conventional example is shown in FIG. In FIG. 11, 1, 2, 3, 4 and 14, 15, 16, 17, 1
8 and 19 are exactly the same as the above-mentioned conventional example.

Reference numeral 20 is a bus receiving circuit of the main unit 1, 21 is a bus driving circuit of the main unit 14 in the same manner, 22 is a common bus transmission line from the main unit to each slave unit, and 23 is a common bus from the slave unit to the main unit. It is a bus transmission line. In this conventional example, each slave device 2,
3, 4 can perform data transmission by forming a data format as shown in FIG. 10, for example, and multiplex-transmitting a data signal for each time slot. However, since the data signals from the plurality of slave devices 2, 3 and 4 are multiplexed on the bus transmission line 23, it is necessary to increase the data transmission rate on the bus transmission line 23.

In this way, even with the high-speed bus connection methods of the first and second conventional examples, it is possible to transfer data of, for example, about 100 MWord / s between electronic device blocks.

[0011]

However, in the first conventional high-speed bus connection method, the slave devices 2, 3, 4 are used.
Since there is a one-to-one connection between the main device 1 and the main device 1, there is a problem that the amount of wiring and the number of bus driving circuits and bus receiving circuits increase. Furthermore, since the physical distances of the bus transmission paths between the master device 1 and the slave devices 2, 3, 4 are different, the phases of the received data signals from the slave devices 2, 3, 4 to the master device 1 are different from each other. However, there is a problem that a circuit such as a FIFO memory (first-in first-out memory) is required to absorb this.

Therefore, as a means for solving the above problem of the wiring amount, there is a second conventional high-speed bus connection method shown in FIG. However, in this case as well, the transmission delay amount from the slave devices 2, 3, 4 to the master device 1 is different, so that the bus receiving circuit 2
In order to match the phase of the data signal at 0, each slave device 2, 3 and 4 is provided with a phase adjusting means, or in the data format of the data signal on the bus transmission lines 22 and 23, guards are provided between the respective time slots. It was necessary to set time.

Therefore, there is a problem that the circuit scale increases or the transmission speed cannot be increased due to the guard time.

The present invention solves the above-mentioned conventional problems, and an object thereof is to provide a high-speed bus extension method which enables high-speed data transmission with a small number of wires and a simple circuit configuration.

[0015]

A first high-speed bus extension method for achieving the above object comprises a main device which is a source of a clock signal and a plurality of slave devices which receive the clock signal from the main device. A high-speed bus extension method in an electronic equipment device configured, comprising: a common clock bus for supplying the clock signal from the master device to the plurality of slave devices between the master device and a plurality of slave devices; A common data bus for transmitting a data signal transmitted from the main device to the plurality of slave devices in synchronization with the clock signal, and each of the plurality of slave devices receiving the data signal transmitted from the main device. A return common data bus for transmitting a data signal output in synchronization with the signal to the main device is provided, and the forward common data bus is common to the forward device from the main device as a starting point. A data signal output from each of the plurality of slaves at each of the plurality of coupling points on the bus, which is connected to each of the plurality of slaves from each of the plurality of coupling points on the data bus. Of the plurality of slaves connected to the forward common data bus, the slave farthest from the master outputs a data signal to the backward common data bus. The connection common data bus is extended from the connection point to be directly connected to the main device and terminated, and the common clock bus starts from the main device and is connected to each of a plurality of connection points on the common clock bus. It is characterized in that the connection form is such that it is connected to each of the plurality of slave devices and is terminated by the slave device at the farthest distance among the plurality of slave devices connected to the outward common data bus.

A second high-speed bus extension method for achieving the above object is an electronic device comprising a main device which is a source of a clock signal and a plurality of slave devices which receive the clock signal from the main device. A high-speed bus connection method in an equipment device, comprising: a common clock bus for supplying the clock signal from the master device to the plurality of slave devices between the master device and a plurality of slave devices, in synchronization with the clock signal. A forward common data bus for transmitting a data signal transmitted by the master device to the plurality of slave devices, and each of the plurality of slave devices receiving the data signal transmitted by the master device are synchronized with the clock signal. And a return common data bus for transmitting a data signal to be output to the main device, and the common clock bus on the common clock bus starts from the main device. A plurality of slave devices connected to each of the plurality of slave devices, and the outward common data bus is the main device as a starting point, and the plurality of slave devices is connected to each of the plurality of slave points on the outward common data bus. And the return common data bus is connected so as to accommodate the data signal output from each of the plurality of slaves at each of a plurality of coupling points on the bus, and the return common data bus is connected to the forward common data bus. Among the plurality of connected slave devices, the slave device that is the farthest from the master device outputs the data signal to the return common data bus, and extends the return common data bus from the coupling point to extend the master device. Connect directly to and terminate the connection,
The common clock bus is connected to each of the plurality of slave devices from each of a plurality of coupling points on the common clock bus starting from the main device, and the plurality of slave devices connected to the outward common data bus. It is characterized in that the connection form is extended from a branch point of the common clock bus to a slave device farthest from the main device among the devices and is directly connected to the main device and terminated.

[0017]

Therefore, according to the present invention, the main unit receives the data signal transmitted from each of the slave units in response to the clock signal transmitted from the main unit and the data signal transmitted in synchronization with this clock signal. In this case, the delay time of the data signal from each slave device with respect to the clock signal is constant regardless of the position of the slave device. Therefore, even if the data bus is extended by adding slave devices, the delay time is synchronized with the clock signal. It becomes possible with a simple circuit configuration.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a bus configuration diagram in a high-speed bus extension method according to claim 1 of the present invention. In the figure, 101
Is an electronic device block that is a main device (hereinafter, main device 101
102, 103, and 104 are electronic device blocks that are slave devices (hereinafter, slave device 102, slave device 103,
It is called a slave device 104).

Reference numeral 105 denotes a common clock bus for transmitting a clock signal from the master device 101 to the slave devices 102, 103 and 104, and 106 denotes a data signal from the master device 101.
02, 103, 104 common outgoing data bus,
Reference numeral 107 designates from the slave devices 102, 103, 104 to the master device 10
It is a return common bus for transmitting a data signal to 1.

108, 111, 112, 114, 11
5, 117, 118 are bus receiving circuits, 109, 110,
Reference numerals 113, 116 and 119 are bus drive circuits.

T1, T2, T3 and T4 are main devices 10 respectively.
1. A coupling point of the slaves 102, 103, 103 and 104 to the common clock bus 105. S1, S2, S3
S4 is the main device 101 and the slave devices 102, 103, 10 respectively.
3, 104 are connection points to the outward common data bus 106. R1 is a data signal input point of the return path data bus 107 to the master device 101, and R2, R3 and R4 are slave devices 10.
2, 103, and 104 are connection points to the return common data bus 107.

L12, L23 and L34 are main and slave devices 101, respectively.
And the slave device 102, between the slave device 102 and the slave device 103, and between the slave device 103 and the slave device 104.

The connecting points T1, S1, and
Although R1, the connection points T2, S2, R2 of the slave device 102, the connection points T3, S3, R3 of the slave device 103, and the connection points T4, S4, R4 of the slave device 104 are separated from each other in FIG. The distance is much smaller than the distances L12, L23, L34 between the respective devices, and the transmission delay time between the respective devices may be approximately L12, L23, L34.

Next, a bus configuration diagram in the high-speed bus extension method according to claim 1 of the present invention will be described with reference to FIG.

A clock signal from a reference clock source (not shown) of the main unit 101 is supplied to a common clock bus 105 at a connection point T1 by a bus driving circuit 110,
Connection points T2, T3 to the slaves 102, 103, 104 are connected.
The bus receiving circuits 111, 114, and
117. The data signal from the main unit 101 is transferred to the forward common data bus 106 at the connection point S1 by the bus driving circuit 109 in synchronization with the clock signal, and the connection points S2, S3 on the forward common data bus 106 are connected.
It branches at S4 and is input to the bus receiving circuits 112, 115, 118 of the slaves 102, 103, 104.

Therefore, the reference clock bus 105 is terminated by the slave device 104 located at the farthest distance from the master device 105 on the outward common data bus 106.

Output data signals from the slave devices 102, 103 and 104 are bus driving circuits 113, 116 and 11 respectively.
Connection point R2 on the return common data bus 107 via
It is sent to the return common data bus 107 by R3 and R4.

The return common data bus 107 extends the return data bus 107 at a connection point R4 from the slave device 104 located farthest from the main device 101 on the outward common data bus 106 to the return common data bus 107. It is directly connected to the input point R1 to the main device 101. In the second conventional bus connection, there is no connection of the return common data bus from the connection point R4 on the return common data bus 107 to the data input point R1 of the main device 101, and the forward common data bus 106
The slave device 102 located closest to the master device 101 above
The connection point R2 to the return common data bus and the data input point R1 of the main unit 101 were connected.

In the description of this embodiment, the number of slave devices is three. However, even when a larger number of slave devices are connected, the common return bus from the slave device farthest from the master device on the outward common data bus 105 is used. The return common data bus is directly input from the connection point to the data bus to the data signal input point of the main device.

Next, FIG. 2 shows a bus configuration diagram in the high-speed bus extension method according to the second aspect of the present invention.

In FIG. 2, the same reference numerals or symbols as those in FIG. 1 indicate the same or corresponding portions as those in FIG. In FIG. 2, 120 is a bus receiving circuit, and the connection point T5 is connected to the bus receiving circuit 120. Common clock bus 10
5 is the main device 10 on the outward common data bus 106.
1 is extended from the connection point T4 for inputting a clock signal to the slave device 104 located farthest from the master device 101.
Is directly connected to the connection point T5 to and is terminated in the bus receiving circuit 120.

FIG. 3 is a circuit configuration diagram in the high-speed bus extension method according to claim 1 of the present invention. In FIG. 3, the slave device 103 is omitted for simplicity.

In FIG. 3, 120 is a reference clock source built in the main unit 101, 121 and 122 are latch circuits built in the main unit 101, 123 and 124 are slave units, and 125 and 126 are slave units. It is a latch circuit built in the device 104. Reference numeral 127 denotes a phase shift circuit that delays the clock signal from the reference clock source 120 of the main device 101 by a certain time and inputs it between the clock input terminals CK of the latch circuits 121. Reference numerals 128 and 129 denote slave devices 102 and 10.
4 is a clock signal line, and 130 is the main device 101.
Internal circuits (not shown) of the slaves 102, 104
Output data signal line of data signal to be transmitted to 131, 1
32 is a data bus 106 common to the outward route from the main device 101.
Input data signal lines for data signals transmitted to the slaves 102 and 104 via the reference numerals 133 and 134.
Reference numerals 02 and 104 are output data signal lines for data signals to be sent to the return common data bus 107 by internal circuits (not shown in particular).

Reference numeral 135 is an input data signal line for a data signal received by the internal circuit of the main device 101 from the slave devices 102 and 104 via the return common data bus 107.

Next, the operation of the main device 101 and the slave devices 102 and 104 in FIG. 3 will be described. The clock signal from the reference clock source 120 of the main unit 101 is put on the reference clock bus 105 at the connection point T1 at the connection point T1 and branched at the connection points T2 and T4 to obtain the bus reception circuits 111 and 11.
7 is taken into the internal circuits of the slaves 102 and 104 through the clock signal lines 128 and 129.

In the main device 101, the data signal is sent from the data signal line 130 to the data input terminal D of the latch circuit 122.
Input to the clock input terminal CK of the latch circuit 122
The signal is output in synchronization with the clock signal from the reference signal source 120 input to the output terminal and is output to the forward common data bus 106 via the bus drive circuit 109.

The data signal on the forward common data bus 106 sent from the main device 101 is first supplied to the slave device 102 at the connection point S2. The data signal input to the slave device 102 is input to the latch circuit 123 via the bus receiving circuit 112, and is taken into the internal circuit of the slave device 102 in synchronization with the clock signal supplied from the main device 101 via the common clock bus 105. Be done.

The data signal on the forward common data bus is also supplied to the slave device 104 at the connection point S4 and input to the latch circuit 125 via the bus receiving circuit 118. It is taken into the internal circuit of the slave device 104 in synchronization with the clock signal from the main device 101 supplied from the reference clock bus 105.

The slaves 102 and 104, which have received the data signal in synchronization with the clock signal from the main device 101, respectively output the output data signal from the internal circuit to the return common data bus 107.

When the data signal from the internal circuit of the slave device 102 is input to the data input terminal D of the latch circuit 124 from the data signal line 133, the data signal is output by the reference clock bus 105 in synchronization with the clock signal supplied from the main device. , Common data bus 1 for the return route via the bus drive circuit 113
It is output to 07.

When the data signal from the internal circuit of the slave device 104 is input to the data input terminal D of the latch circuit 126 from the data signal line 134, the reference clock bus 10 is also generated.
The signal is output in synchronization with the clock signal supplied from the main unit by means of 5, and is output to the return common data bus 107 via the bus drive circuit 119.

The data signals output from the slave devices 102 and 104 pass through the common path for returning data from the connecting point R4 to the main device 101 and the bus receiving circuit 108 of the main device 101. To the data input terminal D of the latch circuit 121.

Clock input terminal CK of the latch circuit 121
The phase shift circuit 127 delays the clock signal from the reference clock signal source 120 for a predetermined time and inputs the clock signal.

By this clock signal, the slave device 10
2, 104 common data bus for the return route
The data signal that has passed through is latched by the latch circuit 121, and the main unit 1 is input by the input signal line 135.
01 to the internal circuit.

The set value of the delay time in the phase shift circuit 127 is supplied to the slave devices 102 and 104 via the forward common data bus 106 with reference to the time point when the data signal is sent from the main device 101, and On the other hand, the slave device 10
The time until the data signal output from each of 2, 2 and 104 reaches the main device 101 via the common return data bus 107 sets the delay time ΔT with respect to the clock signal.

The delay time will be calculated below for each of the slaves 102 and 104 in FIG.

In FIG. 3, bus drive circuits 109 and 11
The circuit propagation delay time of 0, 113, 119 is td, the circuit propagation delay time of the bus receiving circuits 108, 111, 112, 117, 118 is tp, and the latch circuits 121, 122, 12 are shown.
Propagation delay time for the clock signal input of 3,124, 125, 126 is tl, and propagation delay time between the main device 101 and the slave device 102 in the outward common data bus 106 is t.
12, the propagation delay time between slave device 102 and slave device 104 is t
24, tb is the transmission delay time of the transmission line portion from the connection point R4 to the connection point R1 on the return common data bus 107.

(A) In the case of the slave device 102 A data signal is output from the internal circuit of the main device 101 in synchronization with the clock signal from the reference clock source 120 of the master device 101, and is transmitted through the forward common data bus 106 to transmit the slave device. 1
The time ΔT2 from when the data signal is output from the slave device 102 to the slave device 102, which is transmitted through the return common data bus 107, is input to the main device 101, and is output from the bus receiving circuit 108 is as follows.

The delay time of the reference clock signal in the slave device 102 is td + t12 + tp, and the delay time of the data signal from the main device 101 in the slave device 102 is tl + td +.
t12 + tp + tl, the transmission delay time to the connection point R4 on the backward common data bus 107 of the slave device 102 is tl + td
Since it is + t24, ΔT2 = (tl + td + t12 + tp + tl) + (tl + td + t24) + tb + tp = 3tl + 2td + 2tp + t12 + t24 + tb.

(B) In the case of the slave device 104 A data signal is output from the internal circuit of the master device 101 in synchronization with the clock signal from the reference clock source 120 of the master device 101, and is transmitted through the outward common data bus 106 to transmit the slave device. 1
04, so that a data signal is output from the slave device 104 and transmitted through the return common data bus to the master device 101.
Time from the input to the bus receiving circuit 108 and the output from the bus receiving circuit 108
T4 is as follows.

The delay time of the reference clock signal in the slave device 104 is td + t12 + t24 + tp, and the delay time of the data signal from the main device 101 in the slave device 102 is tl +.
td + t12 + t24 + tp + tl, and the transmission delay time to the connection point R4 on the return common data bus 107 of the slave device 102 is tl + td, so ΔT4 = (tl + td + t12 + t24 + tp + tl) + (tl + td) + tb + tp = 3tl + 2td + 2td + 2td + 2td + 2td + 2td + 2td + 2td2t2

As is clear from the above formula of the delay time, the forward common data bus and the backward common data bus are formed by forming the forward common data bus and the backward common data bus as shown in FIGS. 1 and 2. The delay time (ΔT) with respect to the clock signal of the sum of time can be made constant.

This relationship holds even if the number of slave devices increases. Therefore, in the main device 101, the data signal received from the return common data bus 107 via the bus receiving circuit 108 is input to the latch circuit 121, and the clock input CK of this latch circuit 121 receives the reference clock signal source 1
By inputting the clock signal from 20 after delaying it by the delay time ΔT by the phase shift circuit 127,
It will be possible to synchronize with the clock signal.

Next, FIG. 4 is a circuit configuration diagram in the high-speed bus extension method according to claim 2 of the present invention.

In FIG. 4, the same reference numerals or symbols as those in FIG. 3 indicate the same or corresponding portions as those in FIG. In FIG. 4, reference numeral 136 is a clock signal bus receiving circuit.

The common clock bus 105 is extended from the connection point T4 for inputting a clock signal to the slave device 104 located farthest from the main device 101 on the outward common data bus 106, and is connected to the main device 101. It is directly connected to the point T5 and terminated at the bus receiving circuit 136.

Next, the operation of the main device 101 and the slave devices 102 and 104 in FIG. 4 will be described. The operations of the main device 101 and the slave devices 102 and 104 are exactly the same as in the case of claim 1, and therefore the sum ΔT of the delay times of the forward common data bus and the backward common data bus is constant. In this case, the data signal from the return common data bus 107 is transferred to the latch circuit 121.
To the main unit 1 by inputting the clock signal from the connection point T4 on the reference clock bus to the clock input CK.
01 can be incorporated into the internal circuit.

FIG. 5 is an external view when the electronic device blocks are connected by a bus-type common transmission path.

FIG. 6 shows a first high-speed bus extension method according to a third aspect of the present invention. The bus connection structure corresponds to that of the first aspect, and each of a plurality of connection points on the return common data bus 107 is provided. Each of the plurality of slave devices that output the data signal to the output circuit has their output circuits wired-OR coupled to each other.

FIG. 7 shows the second high-speed bus extension method according to the third aspect of the present invention. The bus connection configuration corresponds to the second aspect, and a plurality of connecting points on the return common data bus 107 are provided. Each of the plurality of slave devices that outputs a data signal to each has its output circuit wired-OR coupled to each other. 6 and 7, the same numbers or reference numerals as those in FIG. 3 or 4 indicate the same or corresponding parts.

Further, in FIGS. 6 and 7, 137, 1
40, 141, 143, 144 and 146 are CML (Curr
bus reception circuit using ent mode logic).
8, 139, 142 and 145 are CML (Current Mode L
It is a bus drive circuit using ogic). Each of the plurality of slave devices that outputs a data signal to each of the plurality of connection points on the return common data bus 107 is CML as described in claim 4.
Wired-OR connection is established by a bus drive circuit using (Current Mode Logic).

FIG. 8 shows a concrete circuit configuration of the CML bus driving circuit and the bus receiving circuit. In the present embodiment, the terminating resistance Z0 = 50 ohms allows termination to the ground to speed up the process.

[0064]

As described above, according to the present invention, in response to the clock signal transmitted from the master device and the data signal transmitted in synchronization with this clock signal, each of the plurality of slave devices transmits the signal. When the data signal is received by the main unit,
The delay time of the data signal from each of the slaves with respect to the clock signal is constant regardless of the position of the slave. Therefore, even if the data bus is extended by the addition of slave devices, it is possible to always synchronize with the clock signal, and it is possible to increase the transmission speed of the data bus without adding a circuit. Further, since the bus transmission line is composed of only passive components and each slave device can be connected by wired OR, there is an effect that it is not necessary to stop the operation of electronic device blocks when they are added or removed.

[Brief description of drawings]

FIG. 1 is a bus configuration diagram in a high-speed bus extension method according to claim 1 of the present invention.

FIG. 2 is a bus configuration diagram in the high-speed bus extension method according to claim 2 of the present invention.

FIG. 3 is a circuit configuration diagram in the high-speed bus extension method according to claim 1 of the present invention.

FIG. 4 is a circuit configuration diagram in the high-speed bus extension method according to claim 2 of the present invention.

FIG. 5 is an external view when they are connected by a common bus type transmission line.

FIG. 6 is a circuit configuration diagram in a first high-speed bus extension method according to claim 3 of the present invention.

FIG. 7 is a circuit configuration diagram in a second high-speed bus extension method according to claim 3 of the present invention.

FIG. 8 (a) CML bus drive circuit (b) CML bus receiver circuit

FIG. 9 is a bus configuration diagram showing a first conventional high-speed bus extension method.

FIG. 10 is an explanatory diagram showing a data format on a bus transmission line in a conventional example.

FIG. 11 is a bus configuration diagram showing a second conventional high-speed bus extension method.

[Explanation of symbols]

101 electronic device block 102, 103, 104 which is a main device electronic device block 105 which is a slave device 105 common clock bus 106 forward common data bus 107 return common data bus 109, 110, 113, 116, 119 bus drive circuit 108, 111, 112, 114, 115, 117, 1
18,136 Bus receiver circuit 120 Reference clock source 121,122,123,124,125,126 Latch circuit 127 Phase shift circuit 137,140,141,143,144 CML bus receiver circuit 138,139,142,145 CML bus drive circuit

Claims (4)

[Claims] 1. A high-speed bus extension method in an electronic equipment device comprising a main device that is a source of a clock signal and a plurality of slave devices that receive the clock signal from the main device. A common clock bus for supplying the clock signal from the master device to the plurality of slave devices, and a data signal transmitted from the master device in synchronization with the clock signal to the plurality of slave devices. And a return common data bus for transmitting to the main device a data signal output by each of the plurality of slave devices receiving the information signal transmitted from the main device in synchronization with the clock signal. And the forward common data bus is connected to each of the plurality of slave devices from each of the plurality of coupling points on the forward common data bus starting from the main device. A plurality of return common data buses are connected to accommodate a data signal output from each of the plurality of slave devices at each of a plurality of coupling points on the bus, and are connected to the forward common data bus. Among the slave devices, the slave device that is farthest from the master device outputs the data signal to the return common data bus, extends the return common data bus from the connection point, and directly connects to the master device and terminates. The common clock bus is connected to each of the plurality of slave devices from each of the plurality of coupling points on the common clock bus starting from the main device, and is connected to the forward common data bus. A method of extending a high-speed bus, characterized in that a connection form is established in which the slave device located at the longest distance among the plurality of slave devices is terminated. 2. A high-speed bus extension method in an electronic equipment device comprising a main device that is a source of a clock signal and a plurality of slave devices that receive the clock signal from the main device. Between multiple slaves,
A common clock bus for supplying the clock signal from the master device to the plurality of slave devices, and a forward common data for transmitting a data signal transmitted by the master device in synchronization with the clock signal to the plurality of slave devices. A bus, and a return common data bus for transmitting to the main device a data signal output by each of the plurality of slave devices receiving the information signal transmitted from the main device in synchronization with the clock signal, A common clock bus is connected to each of the plurality of slave devices from each of a plurality of coupling points on the common clock bus with the main device as a starting point, and the forward common data bus is with the main device as a starting point and the forward route. The plurality of slaves are connected to each of the plurality of slaves on the common data bus, and the backward common data bus is connected to each of the plurality of slaves on the bus. A plurality of slave devices are connected so as to accommodate a data signal output from each slave device, and among the plurality of slave devices connected to the forward common data bus, the slave device farthest from the master device is A connection form in which the return common data bus is extended from a connection point for outputting a data signal to the return common data bus and directly connected to the main device and terminated, and the common clock bus is the common device with the main device as a starting point. A slave device which is connected to each of the plurality of slave devices from each of a plurality of coupling points on the clock bus and is the farthest from the master device among the plurality of slave devices connected to the outward common data bus. To the main unit by extending from the branch point of the common clock bus to the main device and terminating the high-speed bus. 3. An output circuit of each of the plurality of slave devices for outputting a data signal to each of the plurality of connection points on the return common data bus is wired-OR coupled to each other. The high-speed bus extension method according to claim 1 or 2. 4. The output circuit is a CML (Current Mode Log).
ic) circuit is used, The high-speed bus extension method according to claim 3.