JP2015154135A - Serial/parallel conversion method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve serial/parallel conversion only by inputting a single line of serial data signal.SOLUTION: A serial/parallel conversion method includes: generating, when receiving two pulses in a time Tpw that starts from the rise edge of a pulse signal included in a serial data signal DIN, a latch signal NLT1 at the fall edge of the second pulse; and generating, when two pulses are not received in the time Tpw, a shift clock signal NSCLK having the rise edge of timing after the lapse of the time Tpw.

Description

  The present invention relates to a serial / parallel conversion method and apparatus for converting a serial signal into a parallel signal, and more particularly to a serial / parallel conversion method and apparatus for receiving data through one signal line.

  Conventionally, in a semiconductor device having a general-purpose output port such as a microcomputer, a serial / parallel converter is used as one means for expanding the number of output ports in order to compensate for the shortage of the number of output ports.

  In a general 8-bit serial / parallel converter 200, as shown in FIG. 4A, an input terminal 1 for a serial data signal DIN, an input terminal 2 for a shift clock signal SCLK, and an input serial data signal DIN are received. The input terminal 3 of the latch signal LT used for finally reflecting the parallel data output signal has three input terminals.

  10 is a shift register circuit configured by eight DFF circuits 11 to 18 and shifts the serial data signal DIN by the shift clock signal SCLK, and 20 latches the contents when 8-bit data is set in the shift register circuit 10. This is a latch circuit composed of eight latches 21 to 28 latched by the signal LT. The output parallel data from the latch circuit 20 is output to the 8-bit output terminal 4.

  In the serial / parallel conversion device 200, as shown in FIG. 4B, the serial data signal DIN sampled at the rising edge of the shift clock signal SCLK is taken into the shift register circuit 10, and after 8 bits have been taken in. The signal is latched in the latch circuit 20 by the latch signal LT and output to the output terminal 4.

  However, when this serial / parallel converter 200 is to be connected to a semiconductor device 50 having a general-purpose output port for expanding the output port, as shown in FIG. 6, the three output ports P2 to P2 of the semiconductor device 50 are used. P4 must be assigned as a control terminal, which is inefficient.

  Therefore, a measure for reducing the number of control terminals required for the serial / parallel converter has been proposed. FIG. 5A is a diagram showing another example of the serial / parallel converter 300 from which one input terminal is deleted (see, for example, Patent Document 1). The serial / parallel converter 300 has only the input terminal 1 for the serial data signal DIN and the input terminal 2 for the shift clock signal SCLK as input terminals. That is, the input terminal of the latch signal LT is deleted.

  The operation of sequentially taking the serial data signal DIN into the shift register circuit 10 based on the shift clock signal SCLK is the same as the operation of the serial / parallel converter 200 described with reference to FIGS. The latch signal NLT2 for fetching the fetched 8-bit serial data into the latch circuit 20 is handled by the DFF circuit 5 by treating the input serial data signal DIN as a clock signal and processing the shift clock signal SCLK as a data signal. Is generated. Note that the addition of the DFF circuit 5 adds a DFF circuit 19 to the shift register circuit 10 in the previous stage.

  Thus, the serial data signal DIN waveform after the arrival of the 8-bit data of the serial data signal DIN and the shift clock signal SCLK so that the serial data signal DIN rises when the shift clock signal SCLK is “H”. If the waveform relationship is set in advance, the latch signal NLT2 of “H” is generated at the latch timing when the reception of 8-bit data is completed. FIG. 5B shows the operation waveform diagram.

JP-A-8-265168

  However, the serial / parallel conversion device 300 described with reference to FIG. 5 has a problem that it cannot be connected with only one output port when attempting to connect to the output port of the semiconductor device 50 described with reference to FIG. 6 having a general-purpose output port.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a serial / parallel conversion device which has only one input terminal for inputting a serial data signal and can use only one output port of a semiconductor integrated circuit having a general-purpose output port. It is to be.

  To achieve the above object, the invention according to claim 1 generates a shift clock signal and a latch signal based on a serial data signal inputted from one signal line, and the serial data signal is generated by the shift clock signal. A serial / parallel conversion method of shifting by m bits (m is an integer of 2 or more), and outputting the m-bit parallel signal by the latch signal after the shift of m bits, wherein the latch signal is When n pulses (n is an integer of 2 or more) are received within a predetermined time starting from the leading edge of the pulse signal included in the serial data signal, the trailing edge of the nth pulse is The shift clock signal is generated when the n pulses are not received within the predetermined time, and the effective edge of the timing when the predetermined time elapses. And generating to have.

  According to a second aspect of the present invention, in the serial / parallel conversion method according to the first aspect, the serial data signal includes a section including a pulse that generates a trailing edge when the predetermined period has elapsed from the leading edge. The first data is a section including a pulse that generates one trailing edge within a predetermined time from the leading edge, and the second data is logically opposite to the first data. The control data is a signal including n pulses that generate n trailing edge edges before the predetermined period of time elapses from an edge edge, and is m bits according to the first data and the second data. It is characterized in that the following data is configured.

  According to a third aspect of the present invention, there is provided an input terminal to which a serial data signal is input, and a one that outputs a shift clock signal having a constant pulse width triggered by the leading edge of the serial data signal input from the input terminal. A shot pulse generation circuit; an m-bit (m is an integer of 2 or more) shift register circuit that sequentially shifts the serial data signal at a trailing edge of the shift clock signal output from the one-shot pulse generation circuit; The number of trailing edges of the serial data signal is monitored during the constant pulse width period of the shift clock signal output from the one-shot pulse generation circuit, and n trailing edges are confirmed (n is 2 or more). A latch signal generation circuit for outputting a latch signal when the output signal is received, and the m-bit parameter output from the shift register circuit. A latch circuit of m bits and outputting Le signal latches I by the latch signal, characterized by comprising a.

  According to the present invention, when a serial / parallel converter is connected to an output port of a semiconductor device having a general-purpose output port, there is an advantage that if one output port is assigned for the serial / parallel converter, the connection can be made. .

It is explanatory drawing which shows the serial / parallel conversion circuit of one Example of this invention, and its operating waveform. FIG. 2 is an explanatory diagram showing a circuit of a one-shot pulse generation circuit constituting the serial / parallel conversion circuit of FIG. 1 and its operation waveform. FIG. 2 is an explanatory diagram showing a latch signal generation circuit constituting the serial / parallel conversion circuit of FIG. 1 and its operation waveform. It is explanatory drawing which shows the conventional serial / parallel conversion circuit and its operation waveform. It is explanatory drawing which shows another conventional serial / parallel conversion circuit and its operation waveform. FIG. 5 is a circuit diagram in which the serial / parallel conversion circuit of FIG. 4 is connected to a semiconductor device having a general-purpose output port.

  FIG. 1 shows a circuit of an 8-bit serial / parallel converter 100 according to one embodiment of the present invention and its operation waveform. Reference numeral 1 is an input terminal for the serial data signal DIN, and 4 is an output terminal for a parallel 8-bit data signal. A shift register circuit 10 includes eight DFF circuits 11 to 18, and shifts the serial data signal DIN by the shift clock signal NSCLK with the “L” pulse. A latch circuit 20 is composed of eight latches 21 to 28. When an 8-bit serial data signal is set in the shift register circuit 10, its contents are latched by a latch signal NLT1. A one-shot pulse generation circuit 30 detects the rising edge of the serial data signal DIN and generates the shift clock signal NSCLK of the “L” pulse. The rising edge of the serial data signal DIN is output again during the output of the “L” pulse. Even if an edge is input, the edge becomes invalid. Reference numeral 40 denotes a latch signal generation circuit. When the falling edge of the serial data DIN is detected twice during the period when the shift clock signal NSCLK generated by the one-shot pulse generation circuit 30 is “L”, the latch signal NLT1 of “H” is detected. Is generated.

  FIG. 2A shows a specific example of the one-shot pulse generation circuit 30 in FIG. In FIG. 2A, 31 is an input terminal for inputting a serial data signal DIN, and 32 is a DFF circuit. The DFF circuit 32 sets the output terminal Q to “H” every time the serial data signal DIN input to the CK terminal rises to “H”, but when the reset terminal RB becomes “L”, the output terminal Q is set to “L”. To. INV1 to INV4 are inverters, and the inverter INV2 is composed of a PMOS transistor MP4 and an NMOS transistor MN3. Reference numeral 33 denotes a constant current circuit that supplies a constant current Ia to the inverter INV2, and includes PMOS transistors MP1, MP2, MP3, NMOS transistors MN1, MN2, and a resistor R1. The value of the constant current Ia is set by the resistor R1. The inverters INV3 and INV4 are connected in reverse parallel via the capacitor C1.

  In the one-shot pulse generation circuit 30, when the reset terminal RB of the DFF circuit 32 is “H”, when the serial data signal DIN rises to “H”, the output terminal Q of the DFF circuit 32 rises to “H”. Is inverted by the inverter INV1, the shift clock signal NSCLK falling to "L" is output from the output terminal 34. Since this signal NSCLK is input to the inverter INV2, the transistor MP4 is turned on, the constant current Ia flows from the constant current circuit 33 into the capacitor C1, and constant current charging of the capacitor C1 is started.

  As a result, when the charging voltage of the capacitor C1 reaches the threshold value Vth3 of the inverter INV3, the inverter INV3 is inverted and the output falls to “L”. When the output of the inverter INV3 falls to “L”, the reset terminal RB of the DFF circuit 32 becomes “L”, the DFF circuit 32 is reset, and its output terminal Q becomes “L”. As a result, the output of the inverter INV1 becomes “H” and returns to NCSCLK = “H”. Further, the transistor MN3 of the inverter INV2 is turned on, and the discharge of the charge of the capacitor C1 is started.

  When the voltage of the capacitor C1 falls below the threshold value Vth3 of the inverter INV3, the output of the inverter INV3 becomes “H”, the reset of the DFF circuit 32 is released, and the serial data DIN can be received. Further, the output of the inverter INV4 becomes “L”, and the capacitor C1 enters a charging standby state.

  The time from when the output of the inverter INV1 becomes “L” to when it returns to “H” is set to Twp depending on the value of the constant current Ia and the threshold value Vth3 of the inverter INV3.

  FIG. 2B shows an operation waveform of the one-shot pulse generation circuit 30. Each time the serial data signal DIN rises to “H”, a shift clock signal NSCLK with a pulse width of Twp is output from the output terminal 34, but before the “L” pulse with the pulse width Twp ends. Since the terminal Q of the DFF circuit 31 is already at “H”, even if the serial data signal DIN rises to “H” again, the edge is ignored.

  3A and 3B show a specific example of the latch signal generation circuit 40 and its operation waveform. 41 is an input terminal for inputting the serial data signal DIN, 42 is an enable terminal for inputting the shift clock signal NSCLK as the enable signal ENB, 43 is an output terminal for outputting the latch signal NLT1, 44 and 45 are DFF circuits, and INV5 and INV6 are It is an inverter.

  In the latch signal generation circuit 40, the serial data signal DIN falls twice to “L” while the “H” continues after the enable signal ENB (= NSCLK) becomes “H”. Then, the Q output of the DFF circuit 45 at the subsequent stage becomes “H”, and the latch signal NLT 1 of “H” pulse is output from the output terminal 43.

を満たせばよい。 In this embodiment, when the pulse width of the “L” pulse of the shift clock signal NSCLK output from the one-shot pulse generation circuit 30 is Tpw, the data indicating “1” of the input serial data signal DIN is “H”. "The pulse width Tw1 of the pulse is

Should be satisfied.

の式（２）、（３）を満たせば良い。Ｔｏｆｆは、“Ｌ”期間のパルス幅である。 The data indicating “0” of the input serial data signal DIN has the pulse width Tw0 of the “H” pulse,

(2) and (3) may be satisfied. Toff is the pulse width of the “L” period.

  Next, the operation of the serial / parallel converter 100 in FIG. 1A will be described in the case where the serial data DIN shown in FIG. 1B is input. The bit sections (1) to (8), which are data sections, are triggered by the rising edge of the serial data signal DIN in each section as a trigger from the one-shot pulse generation circuit 30 to the “L” pulse shift clock signal. NSCLK is output, and the level of the serial data signal DIN is sequentially taken into the shift register circuit 10 at the rising edge of the shift clock signal NSCLK. The 8-bit serial data received from the input terminal 1 is “10111101”.

  Data “10111101” is stored in the shift register circuit 20 when the shift clock signal NSCLK rises in the section (8). Section (9) is control data. Also in this section (9), the shift clock signal NSCLK falling at the first rising edge of the serial data signal DIN is output. In this section (9), the serial data signal falls within the period of the pulse width Tpw of the shift clock signal NSCLK. Since the second falling edge of DIN is input, the latch signal generation circuit 40 outputs the latch signal NLT1 of “H” pulse, and the content of the shift register circuit 10 is received by the latch circuit 20 in response to this. “10111101” is output to the output terminal 4 as a parallel output. Therefore, serial / parallel conversion can be realized only by inputting one serial data signal DIN.

  As described above, in the serial / parallel conversion device 100 of this embodiment, serial / parallel conversion can be realized only by inputting one serial data signal DIN. Therefore, the semiconductor device having the general-purpose output port described with reference to FIG. When connecting the serial / parallel conversion device 100 to 50, there is an advantage that one output port may be assigned to the semiconductor device 50.

1: input terminal of serial data signal DIN 2: input terminal of shift clock SCLK 3: input terminal of latch signal LT 4: output terminal of parallel data signal 10: shift register circuit, 11-19: DFF circuit 20: latch circuit, 21 to 29: Latch 30: One-shot pulse generation circuit, 31: Input terminal, 32: DFF circuit, 33: Constant current circuit, 34: Output terminal 40: Latch signal generation circuit, 41: Input terminal, 42: Enable terminal, 43: output terminal, 44, 45: DFF circuit 50: semiconductor device

Claims (3)

A shift clock signal and a latch signal are generated based on a serial data signal input from one signal line, and the serial data signal is shifted by m bits (m is an integer of 2 or more) by the shift clock signal, A serial / parallel conversion method for outputting the m-bit parallel signal by the latch signal after shifting by m bits,
When the latch signal receives n pulses (n is an integer of 2 or more) within a predetermined time starting from the leading edge of the pulse signal included in the serial data signal, the nth pulse Generated at the trailing edge of
The shift clock signal is generated so as to have an effective edge at a timing when the fixed time has elapsed when the n pulses are not received within the fixed time.
A serial / parallel conversion method. The serial / parallel conversion method according to claim 1,
The serial data signal has, as the first data, a section including a pulse that generates a trailing edge when the predetermined period has elapsed from the leading edge, and one serial data signal within a certain period of time from the leading edge. A section including a pulse that generates a trailing edge is defined as second data having a logic opposite to that of the first data, and n trailing edges are generated before the predetermined period elapses from the leading edge. A serial / parallel conversion method, characterized in that an area including a plurality of pulses is a signal having control data, and m-bit data is constituted by the first data and the second data. An input terminal to which a serial data signal is input;
A one-shot pulse generation circuit that outputs a shift clock signal having a constant pulse width triggered by the leading edge of the serial data signal input from the input terminal;
An m-bit (m is an integer of 2 or more) shift register circuit that sequentially shifts the serial data signal at the trailing edge of the shift clock signal output from the one-shot pulse generation circuit;
The number of trailing edges of the serial data signal is monitored during the constant pulse width period of the shift clock signal output from the one-shot pulse generation circuit, and n trailing edges are confirmed (n is 2 or more). A latch signal generation circuit that outputs a latch signal when
An m-bit latch circuit that latches and outputs the m-bit parallel signal output from the shift register circuit with the latch signal;
A serial / parallel converter characterized by comprising:

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