JP2009205377A - Integrated circuit device having reset control - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit device for matching the reset releasing timing of a plurality of internal circuit blocks. <P>SOLUTION: The integrated circuit device is provided with a first internal circuit block for performing a first reset operation in response to a reset signal and a second internal circuit block for performing a second reset operation different from the first reset operation. The integrated circuit device is provided with: a first internal reset signal generation circuit for outputting a first internal reset signal to the first internal circuit block in response to the reset state of the first reset signal; and a second internal reset signal detection circuit for monitoring a second internal reset signal generated in response to the first reset signal by the second internal circuit block, and detecting that the second internal reset signal has been put into a reset state, and making a reset control circuit put the first reset signal into a release state. The first internal reset signal generation circuit puts the first reset signal into a release state in response to an effect that the second internal reset signal has been put into the release state. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an integrated circuit device having reset control, and more particularly to an integrated circuit device having a plurality of internal circuit blocks having different reset operations.

  The integrated circuit device has a function of resetting the state of the internal circuit in response to power-on or a hardware reset. For example, the internal circuit includes a sequential circuit having a latch circuit for holding data, such as a flip-flop, and a combinational circuit such as a NAND, NOR gate, or inverter. The reset operation includes an operation of resetting the internal state by supplying a reset signal to a latch circuit that holds data, an operation of resetting the internal state of the counter, and the like. When the reset signal is released, the reset state of the internal circuit is released, and the internal circuit starts normal operation in synchronization with the clock.

Regarding the reset operation of the internal circuit, the following patent documents are published.
Japanese Patent Laid-Open No. 2005-322036 JP 2007-52602 A

  A large-scale integrated circuit device has a plurality of internal circuit blocks. When each internal circuit block is configured with a different architecture, each reset operation is different. For example, in response to a reset signal instructing the reset operation of the entire integrated circuit device, the first internal circuit block recognizes the reset signal in a short time and resets the internal state, whereas the second internal circuit The block recognizes the reset signal in a relatively long time and resets the internal state. For this reason, the first internal circuit block first releases the reset state and starts normal operation, but the second internal circuit block still has a state where the reset state has not yet been released. Since a predetermined signal is input / output between the first and second internal circuit blocks, a malfunction occurs between the first internal circuit block during normal operation and the second internal circuit block during reset operation. To do.

  There are various possible causes for different reset operations. For example, when the first and second internal circuit blocks have different internal power supply voltages, the timings at which the internal power supply voltages stabilize are different, and the start and end timings of the reset operation corresponding to the common reset signal are also different. End up. Alternatively, the start and end timings of the respective reset operations may be different because the internal circuit configurations of the first and second internal circuit blocks are different.

  Accordingly, an object of the present invention is to provide an integrated circuit device in which reset release timings of a plurality of internal circuit blocks are matched.

  The integrated circuit device inputs and outputs internal signals between the first internal circuit block that performs the first reset operation in response to the reset signal and the first internal circuit block, and responds to the reset signal. And a second internal circuit block that performs a second reset operation different from the first reset operation. The integrated circuit device further includes a reset control circuit for holding the first reset signal in a reset state in response to the supply reset signal, and the first internal circuit block in response to the reset state of the first reset signal. Monitoring a first internal reset signal generating circuit that outputs a first internal reset signal to the second internal reset signal generated by the second internal circuit block in response to the first reset signal; And a second internal reset signal detection circuit for detecting that the second internal reset signal is in a reset state and causing the reset control circuit to release the first reset signal. Then, the first internal reset signal generation circuit sets the first reset signal to the released state in response to the second internal reset signal being released.

  According to a preferred aspect of the integrated circuit device, the second internal circuit block includes a second internal reset signal generation circuit that generates the second internal reset signal in response to the first reset signal. Have.

  According to a preferred aspect of the integrated circuit device, an internal circuit operates with a first power supply voltage in the first internal circuit block, and is different from the first power supply voltage in the second internal circuit block. The internal circuit operates by the second power supply voltage. The integrated circuit device further includes an internal power supply generation circuit that generates the first power supply voltage and the second power supply voltage from an external supply power supply, and the internal power supply generation circuit supplies the external supply power supply. After the start, the second power supply voltage is set to a rated level after the first power supply voltage.

  In the integrated circuit device of the present invention, the reset release timings of the first and second internal circuit blocks are matched, so that malfunction is avoided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

  FIG. 1 is a diagram illustrating an example of an integrated circuit device. The integrated circuit device LSI has an internal circuit block A and an internal circuit block B. In this example, the internal circuit of the internal circuit block A operates with an internal power supply PW-A of 5V, for example, and the internal circuit of the internal circuit block B operates with an internal power supply PW-B of 1.8V lower than 5V, for example. . The 5V power supply PW-A is the same as the power supply voltage PW of a system (not shown) in which the integrated circuit device LSI is mounted, and the internal circuit block A is an input / output terminal I / O connected to an external circuit device. Connected to. On the other hand, the 1.8V power supply PW-B is generated from the external power supply PW by the power supply generation circuit 10 including a power supply regulator. The internal circuit block B has an internal circuit that uses a low-voltage internal power supply PW-B as a power supply. The internal circuit block B is connected to the internal circuit block A and inputs and outputs internal signals. The signal processing is performed at low speed with low power consumption.

  As described above, the internal circuit blocks A and B configured with different architectures reset the internal circuits in response to the reset signal RST0 generated by the power-on reset circuit 12 when the external power supply PW is turned on, for example. . As shown in the drawing, the internal circuits of both internal circuit blocks A and B have a plurality of flip-flops FF that latch data and a gate G1 that connects them. Then, the respective internal reset signals RST-A and RST-B are inputted to the reset terminals (circled terminals in the figure) of the flip-flop FF, and the respective internal reset signals RST-A and RST-B are in the reset state (H level). In the asserted state), the internal state of the flip-flop FF is reset to an initial state (for example, output Q = H level). When each internal reset signal RST-A, RST-B enters a reset release state (state negated to L level), the reset state of the flip-flop is released, and thereafter the internal circuit blocks A, B The internal circuit starts normal operation in synchronization with a clock (not shown).

  FIG. 2 is a timing waveform diagram showing a reset operation of the integrated circuit of FIG. At time t1, the power-on reset circuit 12 sets the reset signal RST0 to the reset state (H level) in response to the rise of the external power supply PW. The reset state of the reset signal RST0 is an internal reset signal RST-A of the internal circuit block A, which initializes the internal circuit in the internal circuit block A. Then, after the reset period tRA, the reset signal RST0 is released (L level), and the internal reset signal RST-A is also released. As a result, the internal circuit in the internal circuit block A is released from the reset operation and starts normal operation.

  On the other hand, the reset signal RST0 is also supplied to the internal circuit block B. In the internal circuit block B, the internal circuit operates with a 1.8V internal power supply. However, the power supply regulator of the internal power supply generation circuit 10 generates the internal power supply PW-B from the external supply power supply PW, and can raise the internal power supply PW-B to the rated level if a certain time has not elapsed since the power-on at time t0. Can not. Therefore, the internal reset generation circuit 14 in the internal circuit block B sets the internal reset signal RST-B to the reset state (H level) at time t1 delayed for a certain time from time t0. That is, the transition of the internal reset signal RST-B to the reset state is delayed by the time required for the internal power supply PW-B to rise. Along with the recognition delay of the reset signal RST0, the internal circuit block B resets the internal circuit between time t1 and time t3. When reset is released at time t3, the internal circuit in the internal circuit block B starts normal operation in synchronization with the clock.

  As described above, when the integrated circuit device LSI includes the internal circuit blocks A and B having different reset operations, the internal circuit block A performs a normal operation between the times t2 and t3. The reset state is maintained. Since internal signals are input and output between the internal circuit blocks A and B, the internal circuit block A may malfunction. In order to avoid this malfunction, it is required to match the reset operation release timing in both internal circuit blocks A and B.

In the example of FIGS. 1 and 2, the internal circuit blocks A and B have different reset operation periods tRA and tRB with respect to the reset signal RST0 due to the difference in the internal power supply. The reset release timing may be different due to differences in the target circuit or reset operation.
[Integrated Circuit in Embodiment]
FIG. 3 is a configuration diagram of an integrated circuit having reset control in the present embodiment. FIG. 4 is an operation waveform diagram thereof.

  The integrated circuit device LSI has two internal circuit blocks A and B. The internal circuit block A performs a reset operation in response to the first internal reset signal RST-A. The internal circuit block B is connected to the internal circuit block A to input / output an internal signal ISG, and generates a second internal reset signal RST-B in response to the reset signal RST0 to perform a reset operation. The reset operation of the internal circuit block B is different from the reset operation of the internal circuit block A in the operation timing for the same reset signal RST1. In this example, the operation timing is delayed in the reset operation of the internal circuit block B.

  The integrated circuit device LSI has a reset control circuit 20 that holds the first reset signal RST1 in a reset state in response to a supply reset signal RST0 generated by a reset factor such as power-on or software reset. The first reset signal RST1 is supplied to the first internal reset signal generation circuit 22, and the first internal reset signal generation circuit 22 responds to the reset state (H level) of the first reset signal RST1, The first internal reset signal RST-A is set to the reset state (H level). In response to the reset state of the first internal reset signal RST-A, the internal circuit in the internal circuit block A starts a reset operation.

  The first reset signal RST1 is also supplied to the internal circuit block B. In the internal circuit block B, in response to the reset state (H level) of the first reset signal RST1, the second internal reset signal generation circuit 14 resets the second internal reset signal RST-B at time t1. (H level). Thereby, the internal circuit in the internal circuit block B starts a reset operation.

  The second internal reset signal detection circuit 24 monitors whether or not the reset state (H level) of the second internal reset signal RST-B is normally generated and detects that it is normally generated. , The detection signal DTC is output to the reset control circuit 22. In response to the detection signal DTC, at time t2, the reset control circuit 22 sets the first reset signal RST1 to the release state (L level).

  The first internal reset signal generation circuit 22 has the first internal reset signal RST1 released, but the second internal reset signal RST-B is in the reset state (H level). The reset state (H level) of the signal RST-A is maintained. Eventually, at time t3, the second internal reset signal RSTB enters the release state (L level) in response to the release state (L level) of the first reset signal RST1. In response to this, the first internal reset signal generation circuit 22 sets the first internal reset signal RST-A to the release state (L level). That is, at time t3, both the first and second internal reset signals RST-A and B are released, the reset operation of both internal circuit blocks A and B is released, and both internal circuit blocks simultaneously perform normal operation. Start. Therefore, it is possible to avoid a malfunction due to a shift in the reset operation timing of the internal circuit block, particularly a shift in the reset operation release timing.

  FIG. 5 is a specific configuration diagram of the integrated circuit device according to the present embodiment. FIG. 6 is an operation waveform diagram of the integrated circuit device of FIG. FIG. 7 is a diagram showing a specific configuration of the counter operation detection circuit in the integrated circuit device of FIG. With reference to these drawings, a specific integrated circuit device according to the present embodiment will be described in detail below.

  The integrated circuit device LSI of FIG. 5 has a partial LSI-A that operates with a first internal power supply PW-A of 5V, and a partial LSI-B that operates with a second internal power supply PW-B of 1,8V. . The external power supply PW is, for example, a 5V power supply and has the same voltage as the first internal power supply PW-A. An internal power supply generation circuit 10 incorporating a power supply regulator generates first and second internal power supplies PW-A and PW-B from an external supply power supply PW. The internal power supply generation circuit 10 can bring the first internal power supply PW-A to the rated level in a relatively short time in response to the rising of the external supply power supply PW at time t0. On the other hand, the internal power supply generation circuit 10 can bring the second internal power supply PW-B to the rated level only after a time later than the time t0. That is, it takes a certain time for the second internal power supply PW-B to rise.

  On the other hand, the power-on reset circuit 12 detects the rising edge of the external power supply PW at time t0 and sets the reset signal RST0 to the reset state (H level). This reset signal RST0 is a supply reset signal for informing a reset factor.

  In response to the reset state (H level) of the supply reset signal RST0, the reset control circuit 20 holds the first reset signal RST1 in the reset state (H level). As shown in FIG. 7, the reset control circuit 20 includes a reset flip-flop R-FF that inputs a supply reset signal RST0 to a reset terminal. Then, the reset control circuit 20 maintains the reset state (H level) of the first reset signal RST1 until it is detected that the second internal reset signal RST-B has normally transitioned to the reset state.

  The first reset signal RST1 is supplied to both internal circuit blocks A and B. The first internal reset signal generation circuit 22 provided corresponding to the internal circuit block A outputs the first internal reset signal RST-A in response to the reset state (H level) of the first reset signal RST1. Set to reset state (H level). Therefore, the internal circuit in the internal circuit block A starts the reset operation in response to the reset state of the first internal reset signal RST-A at time t0. The first internal reset signal generation circuit 22 is a logical sum circuit that receives the first reset signal RST1 and the second internal reset signal RST-B.

  The first reset signal RST1 is also supplied to the internal circuit block B. In response to the reset state (H level) of the first reset signal RST1, the second internal reset signal generation circuit 14 in the internal circuit block B receives the second internal reset signal at a time t1 after a lapse of a fixed time from the time t0. Internal reset signal RST-B is set to the reset state (H level). Thereby, the internal circuit in the internal circuit block B starts a reset operation.

  The second internal reset signal detection circuit 24 monitors whether or not the reset state (H level) of the second internal reset signal RST-B has occurred normally, and detects that it has occurred normally. . As shown in FIG. 5, a specific configuration example of the second internal reset signal detection circuit 24 is reset by the supply reset signal RST0, enabled by the second internal reset signal RST-B, and synchronized with the clock signal CK. And a counter operation detection circuit 242 that monitors a change in the count output of the counter 240 and detects that the counter normally performs a counting operation for a predetermined period.

  When the internal power supply generation circuit 10 raises the second internal power supply PW-B to the rated level at time t1, the internal circuit in the internal circuit block B starts normal operation. In response to this, the second internal reset signal generation circuit 14 recognizes the reset state (H level) of the first reset signal RST1, and sets the second internal reset signal RST-B to the reset state (H level). To. As a result, the internal circuit block B starts the reset operation as described above.

  The counter 240 is released from the reset state by the release state (L level) of the supply reset signal RST0, and counts in synchronization with the clock CK in response to the reset state (H level) of the second internal reset signal RST-B. Start operation.

  The count operation detection circuit 242 shown in FIG. 7 sets the output to H level when the count value OUT of the counter 240 is “010” and the output to H level when the count value OUT is “101”. An AND gate G12, a flip-flop FF1 reset by the supply reset signal RST0 and set by the output of the gate G11, an AND gate G13, a flip-flop FF2 reset by the supply reset signal RST0 and set by the output of the gate G13, , AND gate G14.

  According to the above configuration, the counter 240 counts when both the release state (L level) of the supply reset signal RST0 and the reset state (H level) of the second internal reset signal RST-B are satisfied. The gate G11 detects the count value “010”, thereby setting the flip-flop FF1, and then the gate G12 detects the count value “101”, thereby setting the flip-flop FF2, and then the gate. G11 detects the count value “010” again, and the gate G14 sets the detection signal DTC to the H level. That is, detecting that the second reset signal RST-B has been in the reset state (H level) for a predetermined period by the counter 240 and the count operation detection circuit 242 is a noise generated during the power-on operation. This means that it is detected that the second reset signal RST-B has normally transitioned to the reset state (H level) instead of the H level of the second reset signal RST-B.

  In response to the H level of the detection signal DTC, the reset control circuit 20 sets the first reset signal RST1 to the release state (L level) at time t2. The first internal reset signal generation circuit 22 maintains the reset state (H level) of the first internal reset signal RST-A by the reset state (H level) of the second internal reset signal RST-B. In addition, the second internal reset signal generation circuit 14 outputs the second internal reset signal RST2 at a time t3 after a predetermined number of clocks after the first internal reset signal RST1 is released (L level). Set to the release state (L level). In response to this, the first internal reset signal generation circuit 22 also sets the first internal reset signal RST-A to the release state (L level). That is, at time t3, the first and second internal reset signals RST-A and B are both released, and both the internal circuit blocks A and B are released from the reset state and start normal operation. Therefore, it is possible to avoid malfunctions of the internal circuit blocks A and B due to a difference in reset operation, in particular, a difference in release timing.

  5 and 7, the boundary between the partial LSI-A operating with the first internal power supply PW-A and the partial LSI-B operating with the second internal power supply PW-B in the integrated circuit device LSI ( A broken line in the figure is provided with a level conversion circuit for converting the signal levels of each other.

  As described above, according to the present embodiment, the reset release timings of the internal circuit blocks having different reset operations in the integrated circuit device are matched, so that malfunction during reset can be avoided.

  The above embodiment is summarized as follows.

(Appendix 1)
A first internal circuit block that performs a first reset operation in response to a reset signal;
A second internal circuit block that inputs / outputs internal signals to / from the first internal circuit block and performs a second reset operation different from the first reset operation in response to the reset signal;
A reset control circuit for holding the first reset signal in a reset state in response to the supply reset signal;
A first internal reset signal generation circuit that outputs a first internal reset signal to the first internal circuit block in response to a reset state of the first reset signal;
The second internal circuit block monitors a second internal reset signal generated in response to the first reset signal, detects that the second internal reset signal is in a reset state, and performs the reset A second internal reset signal detection circuit for causing the control circuit to release the first reset signal;
The integrated circuit device, wherein the first internal reset signal generation circuit sets the first reset signal to a released state in response to the second internal reset signal being released.

(Appendix 2)
In Appendix 1,
The integrated circuit device, wherein the second internal circuit block includes a second internal reset signal generation circuit that generates the second internal reset signal in response to the first reset signal.

(Appendix 3)
In Appendix 2,
In the first internal circuit block, the internal circuit is operated by the first power supply voltage,
In the second internal circuit block, an internal circuit operates with a second power supply voltage different from the first power supply voltage,
And an internal power generation circuit that generates the first power supply voltage and the second power supply voltage from an external power supply,
The integrated circuit device, wherein the internal power supply generation circuit sets the second power supply voltage to a rated level after the first power supply voltage after the supply of the external power supply is started.

(Appendix 4)
In Appendix 3,
The second internal reset signal detection circuit includes a counter that is reset by the supply reset signal and enabled by the reset state of the second internal reset signal, and that the counter has normally counted in a predetermined sequence. A counter operation detection circuit for detecting,
An integrated circuit device that causes the reset control circuit to release the first reset signal when the counter operation detection circuit detects the normal counter operation.

(Appendix 5)
In Appendix 3,
The second internal reset signal detection circuit detects a reset state of the second internal reset signal when the second internal reset signal maintains a reset state for a predetermined period after the supply reset signal is released. Integrated circuit device.

(Appendix 6)
In Appendix 4 or 5,
The first and second internal circuit blocks are integrated circuit devices each having a flip-flop group to which respective first and second internal reset signals are supplied to a reset terminal.

(Appendix 7)
In Appendix 4 or 5,
An integrated circuit device further comprising a power-on reset circuit that detects a rise of the external power supply and resets the supply reset signal for a predetermined period.

It is a figure which shows an example of an integrated circuit device. FIG. 2 is a timing waveform diagram illustrating a reset operation of the integrated circuit of FIG. 1. It is a block diagram of the integrated circuit which has reset control in this Embodiment. FIG. 4 is an operation waveform diagram of FIG. 3. It is a specific block diagram of the integrated circuit device in the present embodiment. FIG. 6 is an operation waveform diagram of the integrated circuit device of FIG. 5. FIG. 6 is a diagram showing a specific configuration of a counter operation detection circuit in the integrated circuit device of FIG. 5.

Explanation of symbols

A, B: first and second internal circuit block 20: reset control circuit 22: first internal reset signal generation circuit 24: second internal reset signal detection circuit RST0: supply reset signal RST1: first reset signal RST-A, B: first and second internal reset signals

Claims (5)

A first internal circuit block that performs a first reset operation in response to a reset signal;
A second internal circuit block that inputs / outputs internal signals to / from the first internal circuit block and performs a second reset operation different from the first reset operation in response to the reset signal;
A reset control circuit for holding the first reset signal in a reset state in response to the supply reset signal;
A first internal reset signal generation circuit that outputs a first internal reset signal to the first internal circuit block in response to a reset state of the first reset signal;
The second internal circuit block monitors a second internal reset signal generated in response to the first reset signal, detects that the second internal reset signal is in a reset state, and performs the reset A second internal reset signal detection circuit for causing the control circuit to release the first reset signal;
The integrated circuit device, wherein the first internal reset signal generation circuit sets the first reset signal to a released state in response to the second internal reset signal being released. In claim 1,
The integrated circuit device, wherein the second internal circuit block includes a second internal reset signal generation circuit that generates the second internal reset signal in response to the first reset signal. In claim 2,
In the first internal circuit block, the internal circuit is operated by the first power supply voltage,
In the second internal circuit block, the internal circuit operates with a second power supply voltage different from the first power supply voltage,
And an internal power generation circuit that generates the first power supply voltage and the second power supply voltage from an external power supply,
The integrated circuit device, wherein the internal power supply generation circuit sets the second power supply voltage to a rated level after the first power supply voltage after the supply of the external power supply is started. In claim 3,
The second internal reset signal detection circuit includes a counter that is reset by the supply reset signal and enabled by the reset state of the second internal reset signal, and that the counter has normally counted in a predetermined sequence. A counter operation detection circuit for detecting,
An integrated circuit device that causes the reset control circuit to release the first reset signal when the counter operation detection circuit detects the normal counter operation. In claim 4,
An integrated circuit device further comprising a power-on reset circuit that detects a rise of the external power supply and resets the supply reset signal for a predetermined period.

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