JPS60132446A - Data signal transfer system - Google Patents

Abstract

PURPOSE:To attain the store of a data terminal synchronous with the data speed for a digital interface device by dividing the data of a data terminal for each fixed number of bits and putting these data on a data link together with a start signal. CONSTITUTION:A certain set value (0 or 1) is always sent to a data link which transmits the data received from a data terminal DTE to a digital extension. The reverse value (0 or 1) of said set value is sent to the data link for each fixed number of bist as a start signal every time the data is received every fixed number of bits from the device DTE. Then the start signal is detected and the subsequent data of a fixed number of bits is extracted. This extracted data is sent to the terminal DTE in response to the speed of the terminal DTE. Thus it is possible to transfer the data signal at an optional speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (11) Technical Field of the Invention The present invention relates to a data signal transfer method in an interface device for accommodating a data terminal to a digital extension line connected to a digital exchange or the like.

(2) Prior Art and Problems A data signal transfer method in a conventional digital interface device will be explained with reference to FIG.

In Figure 1, B DTE is a data terminal, for example,
It has a V24 interface based on the CCITT recommendation standard. LV in the digital interface device DIF is a level exchange section, which performs signal level exchange, and R
4 (i=1 to 5) is a register for exchanging the data signal of the data terminal and the data signal of the digital extension line. In addition, the D/R is a driver/driver for sending signals to the digital extension line and receiving signals from the digital extension line.
The TG, which is a receiver, also generates various timings from the received signal from the digital extension line. This is a timing generation circuit.

Next, the operation of the digital interface device DIF will be explained.

Let's talk about mass and the sending side.

The transmission data sD to be transmitted is stored in the register R1 in accordance with the clock (9,6 KHz) of the transmission timing ST2.
is received serially. The cent signal (1,
6K l1z) is set in register R2. At this time, the request R3 information is also sent to the register R2 as gear information.

The information set in this register R2 is 64Kfiz
This signal is sent to the digital extension line via the driver/receiver D/R. Also, the information in register R2 is cyclically shifted, and the same information (8 bits) is repeatedly sent to the digital extension line until the next register R1 signal is sent. That is,
In this example, the same information is sent five times ((64/1.6)/8 bits).

FIG. 2 shows the digital extension signal sent out from the digital interface device DIF in this manner.

Next, let's talk about the receiving side.

The data signal received from the digital extension line via the driver/receiver D/R is at a speed of 64 kb/s.
Serially received in register R3. As mentioned above, this signal is the same information repeated five times in units of 8 bits, and is set within the same information. and,
Data reception timing RT (9
, 6Ktlz) and serially sends it to the terminal side as received data (RD).In addition, the information in register R5 is sent to the terminal side as carrier detection information (CD).

It can be seen that in such a data signal transfer system, terminals of several data speeds can be accommodated by changing the number of repetitions of the same information on the digital extension line mentioned above. For example, Number of repetitions: 1 time: 48 kb/s 5 times:
9.6 k b/s 〃 10 times: 4.8 kb/s However, conventional signal switching systems can support data rates that are an integer fraction of 48 k b/s;
The problem is that data rates that are not fractions of an integer, such as 19.2 kb/s, cannot be supported.

(3) Object of the Invention An object of the present invention is to make it possible to accommodate synchronous data terminals with data rates that could not be transferred conventionally.

(4) Structure of the Invention In order to achieve the above object, the present invention provides an interface device connected to a digital extension line of a digital exchange and accommodating a synchronous data terminal, in which data received from the data terminal is sent to the digital extension line. A certain set value (0 or 1) is normally sent to the data link, and every time a certain number of bits of data are received from the data terminal, the inverted value of the set value is sent to the data link as a start signal, A means for transmitting a fixed hint, and subsequently transmitting data received from the data terminal, and detecting the start signal from the data link from which data is transmitted as described above from the interface device of the communicating party, and The present invention is characterized by having means for extracting the following data of the fixed number of bits and transmitting the data to the data terminal in accordance with the speed of the data terminal.

(5) Examples of the invention Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 3 is a configuration diagram of an embodiment of the present invention.

In FIG. 3, Ri (+=6 to 10) is a register added to support a data rate that cannot be supported by the conventional method, and F□ and F2 are flags.

DIV is a differential signal generation circuit, G is a gate 1-, and SEL is a selector. Also, TG' is R1 to R1 as in the conventional method.
1 (timing for operating 5 (however, in Figure 3, the shift clock of R1 and 'R4 is 43 kb/s
It is. ) and Ri (i=6-i.

) is a timing generation circuit that generates the timing to operate. The rest is the same as that shown in FIG. 2 described in connection with the conventional method.

Next, the data transfer power formula according to the present invention will be specifically explained.

First, the transmitting side will be explained.

Transmitted data from data terminal D"r"E is received serially at data rate into register R6.

When 8 hits are received in register R6, the contents of register R6 are changed to register R7 by cent signal t/8.
The contents of register R7 are 48 kb/
s to register R1. At this time, register R7
1 and 0 bits are set at the beginning of register R7, and after the data in register R7 is shifted out, 1 is loaded, so register R7 is transferred from register R6 to register R.
Every time a data sensor I~ to 7 is performed, the received data from the data terminal with a 0 added in front (8 pino days) will be sent out, otherwise 1 will be sent out.

Note that the process by which the output of register R7 is sent to the digital extension line is the same as in the prior art, and will therefore be omitted.

The output of R7 is not shown in Figure 4-.

Next, the receiving side will be explained.

The signal received from the digital extension line is divided into carrier information and a 48 kb/s bit string in the same manner as in the conventional system, and this bit string (output of register 7, i.e., similar to FIG. 2) is serially sent to register R8. Received.

Then, when the O added in front of the valid data (8 bits) is shifted to the d-bit position of register R8, the contents of register R8 are set to register R9, and flag F1 is set. Ru. Further, the differential signal generating circuit DIV generates a differential signal from the output of the flag Fl, thereby setting all the values in the register R8 to 1.

This is to prevent the same I-- from register R8 to register R9 from being performed at 0 bit in the valid data.

Furthermore, the data in register R9 is transferred to register Rl by set signal t/8 or t/8 selected by selector SEL.
The data is sent to O and output at the data rate depending on the data rate. Note that the cent signal is selected from the cent signal from register R8 to register R9 and from register R.
If the timing of setting from 9 to register RIO is almost equal,
To avoid missing data or duplication,
This is so that when such a situation occurs, the signal sent from register R9 to register R10 can be changed to a signal with a 180° phase shift.The gate G is used to realize this. , flag Fz.

That is, when the sen1~ signal is generated in the reset state of the flag F1, the value of the flag F2 is inverted, thereby changing the output of the selector 5EI-.

According to the above-described embodiment of the present invention, the data terminal speed can take any value below 38.4 (48x8/N0) kb/s, which is a data speed that could not be accommodated by conventional methods. This has the effect of accommodating data terminals.

As explained above, the present invention makes it possible to transfer data signals at any speed by dividing data from a data terminal into units of a fixed number of bits, adding a start signal, and transmitting the data onto a high-speed data link. Since data terminals with data speeds that could not be accommodated in the past can now be accommodated, the efficiency of the data communication function is improved.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a conventional digital interface device, and FIG. 2 is an explanatory diagram as an example of a sending signal. FIG. 3 is a block diagram of an embodiment of the digital interface device according to the present invention, and FIG. 4 is an explanation of an example of the received signal shown in FIG. RlL-R. : Register D/Rl time/receiver "I"G' : Timing generation circuit DIV : Differential signal generation circuit Fl, F2 : Flag SEL : Selector

Claims (1)

[Claims] In an inkface device connected to a digital extension of a digital exchange and accommodating a synchronous dream data terminal,
A certain set value (0 or l) is always sent to the data link that sends the data received from the data terminal to the digital extension line, and every time a certain number of bits of data are received from the data terminal, the data link is sent to the data link. , a means for transmitting a constant bit using the inverted value of the set value as a start signal, and subsequently transmitting received data from the data terminal; detecting a start signal and extracting data for the constant number of binods following it;
It also includes a means to send that data to the data terminal at the speed of the data terminal.