JPS598101B2 - In-station transmission path monitoring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fault monitoring system for a transmission line in an intra-office universal format transmission section of a digital data transmission system using a centralized clock system.

To facilitate understanding of the following explanation, some terms will first be explained.

FIG. 1 is a diagram for explaining a centralized clock, and a digital clock supply device 1 is a digital clock supply device (hereinafter referred to as DCS) that supplies clock signals synchronized in frequency and phase to various digital devices in the station. ). The in-office line termination device 2 is 3.2, 6.4, 12
．． A digital data signal having a transmission rate of 8, 6.4 Kb/S is converted into a 64 Kb/S universal format signal, which will be described later, or vice versa. The in-office line termination device 2 is connected to the multiplexing device 3 via the in-office transmission line 4, and the signal from the device 2 is converted into a 64 Kb/S multiplexed signal. A clock signal from clock supply device 1 is supplied to in-office line termination device 2 and multiplexer 3 through clock signal transmission line 5. The multiplexed signal is transmitted to transmission line 6. A subscriber line is connected to the in-office line termination device 2, and the waveform, level, etc. of the signal between the subscriber terminal 9 and the subscriber line T are converted by the subscriber line termination device 8. A clock supply device 1, an in-office line termination device 2, a multiplexing device 3, and transmission lines 4 and 5 constitute an in-office system. What is the centralized clock system? As shown in Figure 1, a clock transmission path is provided independent of the information signal transmission path (digital data). The method of supplying

FIG. 2 is a diagram for explaining an envelope format often used in data transmission at present.

The envelope format divides the data to be transmitted into 6 bits (D1 to D6 in the figure), and divides the data into 6 bits (D1 to D6 in the figure), and uses synchronization frame bits (referred to as F bits) F and subscriber terminals to supply a clock to the terminal side in the subscriber section. This refers to a signal format in which S is surrounded by status bits (referred to as S bits) for indicating network status, etc. FIG. 3 is a diagram for explaining the universal format. In Figure 3, 10 indicates a transmission rate of 6.4Kb.
/S envelope format information signal bit string 11 is a bit string with a transmission rate of 64 Kb/S that is obtained by converting information signal bit string 10 into the universal format, and has exactly the same content as the 8-bit envelope format information signal. 8 with
It consists of a bit dummy D. Reference numeral 12 denotes a frame clock signal supplied from the digital clock supply device 1 and providing the F bit position in the universal format.

The universal format will be explained below with reference to FIG. In universal format, 6.4 Kb/s information signal 10
The speed is converted to 64 Kb/S in envelope units and inserted into the position indicated by I in the bit string 11, and an envelope exactly the same as I is inserted into the following 72 bits, that is, a time slot corresponding to 9 envelopes. As explained in the example above, the universal format is an information signal that repeats the same envelope multiple times within a certain time, more precisely the number of times that the transmission speed of the universal format is divided by the transmission speed of the information signal converted into it. Refers to the transmission format of FIG. 4 shows the ratio of I and D for each information signal speed. Further, in the centralized clock system, the F bit phase of each envelope in the universal format matches the phase of the frame clock supplied from the clock supply device 1. Now, in the conventional universal format transmission in the internal station system of the centralized clock system, the F bit position can be determined by the frame clock from the clock supply device 1, and there is no need to transmit the frame pattern. F as shown in
The F bit at the bit position is always removed and set to O, and is not used as an information signal at all.

By the way, in the current data transmission system, it is possible to use an all-zero signal as an information signal, where the data Di (1 = 1, 2, 3...) in the envelope is all 0, and the S bit is also O. Similarly, the signal received in the event of a failure such as a disconnection or short circuit in the intra-office transmission line is also an all-zero signal. Therefore, the conventional system has the disadvantage that it is not possible to distinguish between an information signal due to all zero signals and a fault in the intra-office transmission line, and that a fault in the intra-office transmission section cannot be detected by monitoring the information signal transmission line. In order to eliminate the above-mentioned drawbacks in the universal format signal transmission in the current centralized clock system, this invention inserts a pattern other than all zeros into the F bit position and monitors this pattern to improve the internal transmission. This system is characterized by detecting road obstacles.

FIG. 6 shows an embodiment of the intra-office transmission line monitoring system according to the present invention, and the same reference numerals are given to the same parts as in FIG. 1.

This is a case where the present invention is applied to a pair of reciprocating universal type information signal transmission lines 13 and 14 in the intra-office transmission line 4. The sending end side in the in-office line termination device 2, that is, the transmission line 1
3 is connected to the F bit pattern insertion circuit 15 on the receiving end side,
That is, the F bit pattern detection circuit 16 is connected to the transmission line 14. In the multiplexer 3, an F bit pattern insertion circuit 17 is connected to the sending end, that is, the transmission line 14, and an F bit pattern detecting circuit 18 is connected to the receiving end, that is, the transmission line 13. Further, in this example, the F-bit pattern insertion circuits 15 and 17 are controlled through respective control lines 21 and 22 depending on the detection state of the F-bit pattern detection circuits 16 and 18. In FIG. 6, the universal format signal generated by the in-office line termination device 2 has all one pattern inserted into the F bit position by the F-bit pattern insertion circuit 15, and is sent to the multiplexing device 3 via the in-office transmission line 13. transmitted.

In the multiplexer 3, an F bit pattern detection circuit 18 detects and monitors the F bit pattern. F when normal
The bit pattern detection circuit 18 detects, for example, an F bit pattern of 1'' in total.Suppose that the information to be transmitted is data D.
Even if both i (1-1, 2...) and S bit are o, even if a failure occurs due to disconnection or short circuit in the intra-office transmission line 13, all zero signals will be generated at the receiving end of the multiplexer 3. is received, but
In the case of a failure, the F-bit pattern detection circuit 18 will of course be unable to detect the normal F-bit pattern (all 1s), allowing the multiplexer 3 to detect the failure in the intra-office transmission line 13. If a fault in a transmission path can be detected not only by the device at the receiving end but also by the device at the sending end, the fault can be dealt with more quickly. Therefore, when the F-bit pattern detection circuit 18 of the multiplexer 3 detects a fault in the intra-office transmission line 13, it controls the F-bit pattern insertion circuit 17 via the control line 22, which inserts the F-bit pattern into the intra-office transmission line 14. A pattern different from the pattern (all 1s) inserted during normal operation, for example, a repetition of "1" and "0" is assumed. When the F bit pattern detection circuit 16 in the intra-office line termination device 2 detects this F-bit pattern, the intra-office line termination device 2 can also recognize a fault in the intra-office transmission line 13. In this case, the F bit pattern detection circuit 16,1
8 is capable of detecting two types of patterns. Although the case where a failure occurs in the intra-office transmission line 13 has been described above, the case where a failure occurs on the intra-office transmission line 14 is exactly the same.

In order to simplify the circuit configuration, the F bit pattern detection circuits 16 and 18 may detect only one type of pattern. The operation shown in FIG. 6 in this case will be described below. A failure occurs in the intra-office transmission line 13 and the F bit pattern detection circuit 18
When detecting that all F bits are 0'', the F bit insertion circuit 17 is controlled via the control line 22, and the multiplexer 3 transmits the signal to the in-office line termination device 2 via the in-office transmission line 14.
Let all F bits of the universal signal transmitted to 0 be 0. The F bit pattern detection circuit 16 in the intra-office line termination device 2 detects that the F bits are all zeros, and detects that a fault has occurred in the intra-office transmission line 13 or 14. By doing this, a fault in the intra-office transmission line 13 or 14 can be detected by both the intra-office line termination device 2 and the multiplexer 3.
However, in this case, it is not possible to determine which of the intra-office transmission lines 13 or 14 is at fault. Note that it is usually not appropriate to use the framing bit pattern of the subscriber transmission line 7 for monitoring the intra-office transmission line 4. This is because the framing bit pattern P1 and O in the subscriber transmission line 7 is usually repeated. By the way, in the universal format, as described in FIG. The bit positions 21 are all zeros, all zeros, and all ones, and this pattern changes depending on the signal speed of the subscriber transmission line 7. For example, if the signal speed of the subscriber transmission line 7 is 6.4 Kb/S, the F bit pattern in the universal format is 1111111111000.
0000000 is repeated, but if the signal speed of the subscriber transmission line 7 is 12.8 Kb/S, it is 111110
0000 will be repeated.

This means that the monitoring pattern that is considered to be normal is not unified within the station, making it complicated, and especially if the signal speed of the subscriber transmission line 7 is slow, the all-zero pattern can easily be mistaken for a fault, and fault detection is difficult. It becomes complex and failures cannot be dealt with quickly. However, in the present invention, as described above, by uniformly transmitting frame patterns using the frame pattern insertion circuits 15 and 17, fault detection can be easily and quickly performed.
As explained above, according to the present invention, the in-office transmission line is constantly monitored by using the envelope-format F bit that is not used for information transmission on the transmission line that transmits the universal format signal in the centralized clock system. This makes it possible to quickly take measures such as detecting and searching for failures, thereby improving the operating rate and reliability.

[Brief explanation of drawings]

Figure 1 is a diagram to explain the centralized clock system, Figure 2 is a diagram to show the envelope currently used for data transmission, Figure 3 is a diagram to explain the universal format signal, and Figure 4 is a diagram to explain the universal format signal. A diagram showing the relationship between I and D with respect to various information signal speeds, FIG. 5 is a diagram showing the current universal format signal with all F bits set to 0'', and FIG. 6 is a block diagram showing an embodiment of the present invention. 1: Clock supply device, 2: In-office line termination device, 3: Multiplexing device, 4: In-office transmission line, 5: Clock transmission line, 6:
Multiplexed signal transmission path, 7: subscriber line, 8: subscriber line termination device, 9: subscriber terminal, 10: envelope format data signal, 11: universal format signal, 12: frame clock, 13, 14 : Internal transmission line, 15, 17: Frame pattern insertion circuit, 16, 18: Frame pattern detection circuit, 21, 22: Control line.

Claims (1)

[Claims] 1 A digital data transmission method that transmits information as one envelope, consisting of framing bits used for envelope synchronization, several data bits, and status bits used to indicate the status of information in the envelope, and that uses the same clock. In the universal signal format for centralized clock intra-office transmission, which supplies a clock from the source to each transmission device, a pattern containing "1" other than all logic zeros is used to transmit envelope information on the sending end to the sending end device at its framing bit position. and means for detecting framing bits of envelope information transmitted from the sending end device to the sending end device via the intraoffice line. In-station transmission path monitoring method.