JPH0435937B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission system for clock and frame signals in digital communication systems and the like.

In synchronous systems such as digital communication systems, a dependent synchronization method as shown in Figure 1 is generally used for reasons such as preventing slips within the system and centralizing high-precision phase-locked oscillators. be. That is, as shown in FIG. 1, clock and frame signals 2 whose phases are controlled by a clock and frame supply device 1 are supplied to each peripheral device 3 to 5, and each peripheral device 3 to 5 receives its clock and frame signal. A method is adopted in which synchronous operation is performed according to signals.

In the clock distribution system in the system as shown in FIG. 1, the frame signal as shown in FIG. 2 is used because the bit error rate is considered to be sufficiently low and the circuit configuration is relatively simple. 11, transmission code rule violation 14
Generally, the transmission code 13 is superimposed on the clock signal 12 to create and transmit the transmission code 13. In addition, in Fig. 2, as an example, 7
A case is shown in which a frame signal 11 for each bit is transmitted by violation 14 of a bipolar code. As described above, although the method of transmitting a frame signal by violation has several advantages as described above, according to the prior art, the type of frame signal that can be transmitted is limited to one type. Therefore, when transmitting a plurality of types of frame signals whose frequency ratios are not integers, it is necessary to physically transmit them through a plurality of transmission paths, as shown in FIG. That is, as shown in FIG. 3, the frame signal 11 of every 7 bits is
When transmitting the frame signal 15 of every 3 bits by superimposing it on the clock signal 12 by violation of the transmission code rule, each frame signal 11, 15
It was necessary to create transmission codes 13 and 16 based on violations 14 and 17 corresponding to the above, and to transmit them through separate transmission paths so that they would not be mixed.

Therefore, in the case of such a system using separate transmission lines, a plurality of physical transmission lines are required. Furthermore, delay variations due to different transmission paths lead to disadvantages in system configuration, such as limitations on the transmission area.

It is an object of the present invention to eliminate the drawbacks of the conventional system described above, and to use, for example, an 8KHz frame, which is the basic frequency of a time division switch, and TCM (Time Compression) in an ISDN switch.
Multiplexing system, such as distributing frames of different frequencies used for subscriber line digital transmission.
Even when it is necessary to distribute multiple types of frames, by transmitting multiple types of frame signals through a single physical transmission line, the clock frame signal distribution system can be simplified and the implementation can be more flexible. The objective is to provide a frame signal transmission method that allows for

The gist of the present invention is to create a logical sum signal of a plurality of types of frame signals on the transmitting side, transmit the logical sum signal by violation of the transmission code rule, and perform violation of the transmission code rule on the receiving side. The purpose of this method is to detect each frequency of a plurality of types of frame signals based on the detected signal and a clock signal, and reproduce the corresponding frame signals.

The present invention will be explained in detail below with reference to the drawings.

First, one of the frame signal transmission methods according to the present invention
An example will be explained using a time chart shown in FIG. In this embodiment, the first frame signal 11 is a signal that repeats every 7 bits, and the second frame signal 15 is a signal that repeats every 3 bits. On the sending side, a signal 18 which is the logical sum of these two frame signals 11 and 15 is generated.
is generated, this signal 18 is superimposed on the clock signal 12, and a code 19 obtained by applying a violation 20 to the transmission code is sent to the transmission path. On the receiving side, a violation is detected from this transmission code 19, a violation detection output 21 is obtained, and a frame signal detection circuit, which will be described later, reproduces first and second frame signals 22 and 23. Here, the method of creating the OR signal 18 on the sending side, the method of creating the transmission code 19 by violation, and the method of obtaining the violation detection output 21 from the transmission code 19 can be easily accomplished. The following is the violation detection output 21.
A circuit configuration for reproducing a frame signal based on the following will be explained with reference to FIG.

FIG. 5 shows an embodiment of the frame signal detection circuit described above, in which the second frame signal (frame signal every 3 bits, 15 in FIG. 4) detection circuit 30
and a first frame signal (frame signal every 7 bits, 11 in FIG. 4) detection circuit 40. Further, 12 is the aforementioned clock signal, and 21 is a violation detection signal on the receiving side. Each block 30, 40 has a frame counter 3 that counts the interval between frames.
1, 41, AND gates 33, 43 for resetting the frame counters 31, 41 using the violation detection signal 21 in the event of an error; AND gates 34, 44 for frame abnormality detection to detect the absence of the violation detection signal 21; error counters 32, 4 to count the number of frame abnormalities;
2. AND gates 35, 45 for error count enable to create count enable conditions for error counters 32, 42; OR gates 36, 46 for creating error counter reset conditions to create reset conditions for error counters 32, 42; violation detection signal 21; and reset conditions (gate 36,
46 output signal), the error counter 33,
42, and consists of AND gates 37 and 47 for resetting error counters. Also,
The second frame signal detection circuit 30 has a frame normality detection ungate 38 that detects the presence of the violation detection signal 21 at every period (3 bits) determined by the frame counter 31.

The operation of the circuit shown in FIG. 5 will be explained below. First, the operation of the second frame signal detection circuit 30 will be described.

First, when the period is off, the error counter 3
2 is "1", and when the violation detection signal 21 becomes "1", the gates 33, 3
6 and 37, both the frame counter 31 and error counter 32 are reset (draw-in start state). Thereafter, the frame counter 31 starts counting the clock signal 12, outputs the second reproduced frame signal 23 at every expected frame interval (3 bits), and detects the presence or absence of the violation detection signal 21 in each frame. Judgment is made by the abnormality detection AND gate 34. If the violation detection signal 21 continues to arrive at intervals of every three bits, the output of the frame abnormality detection gate 34 remains at "0" (synchronized state). on the other hand,
When there is no violation detection signal 21 (“0”) at the expected interval (3 bits), the output of the frame abnormality detection gate 34 changes to “1”.
The error counter 32 is incremented by the enabling condition of the error counter enable gate 35. However, in the example of FIG. 5, since the front three stages are protected, the second reproduction frame signal 23 continues to be output at the same cycle as before (forward protection state). If the output of the frame abnormality detection gate 34 is "1" for three frames, the output of the error counter 32 is "1".
(out-of-synchronization state), and the next time the violation detection signal 21 becomes “1”, the gate 3
frame counter 31 via 3, 36, 37;
Both error counters 32 are reset (re-retraction start state).

The operation of the first frame signal detection circuit 40 is also similar to the operation of the second frame signal detection circuit 30, and the first reproduced frame signal 22 is output. However, the frame period to be detected by the first frame signal detection circuit 40 is every 7 bits, and the second
Since the second frame signal detection circuit 30 is longer than that of the frame signal detection circuit 30, the second frame signal detection circuit By inputting the output of the frame normality detection gate 38 in the circuit 30 to the violation pull-in gate 43, the invalid violation detection signal 21 is suppressed.

By the above operation of the frame detection circuit, the first,
From the violation detection signal which is the logical sum of the second frame signals 11 and 15, it is possible to separate and reproduce each of the first and second frame signals.

In this embodiment, the frame signal period is 3 bits and 7 bits, the frame signal type is 2 lines, and the transmission path code is a bipolar code. for the frame signal, or
It is clear that the present invention is also applicable to other code rules such as CMI (Code Mark Inversion).

In addition, in this embodiment, the signals to be transmitted are limited to clock and frame signals, but three types of signals, clock, frame signal, and data, can be transmitted through one transmission path.
It goes without saying that the present invention is applicable to a transmission system in which multiple types of frame signals are transmitted.

As explained above, according to the present invention, it is possible to physically distribute a clock and multiple frame signals through one transmission line, and it is only possible to reduce the number of transmission lines for distributing clock frame signals. Instead, it becomes possible to avoid implementation constraints due to delay variations between transmission lines that occur when multiple transmission lines are used, and flexibility in system configuration can be expected.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a clock and frame signal distribution system in a synchronous system such as a time division switch, and FIG. 2 is a time chart showing a method of transmitting a frame signal by superimposing it on a clock by violation. Figure 3 is a time chart showing a conventional method in which two types of frame signals are transmitted via separate transmission paths by being superimposed on the clock due to violation. Figure 4 is a time chart showing two types of frame signals being transmitted through one 5 is a time chart showing an example of the method of the present invention in which a frame signal is transmitted superimposed on a clock due to a violation through a transmission path. FIG. 5 is a block diagram showing an embodiment of a frame signal detection circuit in the present invention. It is. 11: First frame signal, 15: Second frame signal, 12: Clock signal, 18: OR signal of first and second frame signals, 13, 16, 1
9: Transmission code, 14, 17, 20: Violation, 21: Violation detection signal, 22,
23: first and second reproduction frame signals, 30, 4
0: Frame signal detection circuit, 31, 41: Frame counter, 32, 42: Error counter, 38
~38, 43-47: Gate.

Claims (1)

[Scope of Claims] 1. A transmitting side device that generates and outputs a clock signal and first and second frame signals having different frame intervals, and a receiving side device that receives the clock signal and the first and second frame signals. The transmission side device superimposes the first and second frame signals on the clock signal according to a violation of the transmission code rule to create a transmission code, and the transmission code is sent to the reception side device. In the frame signal transmission method to be transmitted, a connection means is provided for connecting the transmitting side device and the receiving side device through a single transmission path, and the receiving side device detects a violation of the transmission code. and frame signal reproducing means for reproducing the first and second frame signals, respectively, the frame signal reproducing means comprising first and second frame signal detecting sections, and detecting each of the frame signals. The unit includes a frame counter that starts counting the clock signal when the violation is detected and outputs a reproduced frame signal every frame period of the frame signal, and a frame counter that detects the violation that matches the reproduced frame signal. a counter reset means for resetting the count value of the frame counter when there is no signal and this state continues for a predetermined number of frames; A frame signal transmission system characterized in that it includes means for repeating each counting operation of a clock signal.