RU1835545C - Device for data interchange between computer and users - Google Patents

Abstract

The invention relates to the field of computer technology and may used in the construction of computer systems. The goal is to increase the reliability of the reception and transmission of information. The device includes a block of transceivers, a block of receivers and transmitters of control signals, an error detection block, an encoder, a memory register, a status register, two selectors, an oddness control unit, four formers; one-shot, counter, control unit, multiplier, generator. 3 silt

Description

Yo

The invention relates to the field of computer technology and can be used in the construction of computer systems and control systems for communications in automatic telephone exchanges, as well as in systems for collecting, processing and exchanging information.

The aim of the invention is to increase the reliability of the data transfer process.

Figure 1 presents the electrical structural diagram of a device for the exchange of information between computers and subscribers; Fig. 2 is an electrical functional diagram of an error detection unit; Fig. 3 is an electrical functional diagram of a distributor.

The device comprises a transceiver unit 1, a control signal receiver unit 2, a control signal transmitter unit 3, an error detection unit 4, an decoder 5 (addresses), a memory register 6, a state register 7, a distributor 8, a pulse shaper 9, a distributor 10 Oddness control unit 11, one-shot 12. Counter 13, synchronization unit 14, multiplexer 15, control bit shaper 16, clock pulse generator 17, shapers 18, 19 time intervals, receiver blocks 20.1, 20.2, transmitter block 21 in the communication line with subscriber s, computers Highway 22, line 23 interrupts.

. The error detecting unit 4 contains a D-flip-flop 24, a group of elements EXCLUSIVE OR 25, a group of elements OR 26. OR element 27.

00 Сл) (Л СП

4

01

Distributors 9, 10, each contains a counter 28, a decoder 29, a group of elements NOT 30, an element OR 31.

The blocks of receivers 20.2 and transmitters 21 are connected by inputs and outputs to subscriber group lines, respectively.

A device for exchanging information between computers and subscribers works as follows.

After turning on the supply voltage, an initial setting signal (NU) is supplied to input 1 of synchronization unit 14 (Fig. 1), by which unit 14 generates a reset signal (from output 2) (zero) for blocks 4.8, 10 and 13.

The device is ready for the exchange of information, which is carried out through a centralized channel (trunk) between subscribers and the computer trunk in two modes of RECORDING and READING using the mode signal CCht / KZp generated from the output 7 of block 14.

In the RECORD mode from the side of the computer, the address code for identifying the direct device is issued to the decoder 5 to the decoder 5 and simultaneously, in block 1, the address code of the subscriber to which information from the computer is to be recorded (output).

From the outputs of the decoder 5, a decoded signal is supplied to block 6, which is recorded in block 6 upon receipt of the front of the VDS control signal from the computer via line 22 through the receiver block 2.

Upon the arrival of this signal from the output 1 of block 2 to block 6, the latter generates a response control signal DVM-A, which is issued through the block of transmitters 3 via line 22 to the computer.

Simultaneously, from the output 1 of block b, a signal is sent to block 1, through which the subscriber's address code (byte) is recorded in block 1.

The data (four bytes) issued by the computer via line 22 enters block 1 in the next phase of time and is written to it upon arrival of the write control signal (Cn) from the computer. This signal comes from the output 2 of block 2 to the input 1 of block 1. At the same time, the control bit of each byte is transmitted to the subscriber.

Block 4 (Fig. 2) checks the information of the control bits and, in case of error, generates an error signal in register 7 (Fig. 1), the state of which is then read by the computer.

From the outputs of block 1, information is transferred byte-by-byte (first byte of the address, then four bytes of data) to the transmitter block 21 and from it by a bipolar phase signal along symmetrical output lines to the subscriber. At the same time, for each information byte in block 16, a control bit is generated and, on a separate line, the RRC signal

transmitted along with the data (address) to the subscriber.

The reading of each byte of information from block 1 is carried out using control signals generated by the distributor 0 by the body 8 (Fig. 3). to the counting input of which the signal from the output 4 of the synchronization block 14 (Fig. 1) is received, the same block 14 generates from the output 8 (when transmitting each byte) a strobe signal P.K to the block 5 of sensors 21 for reliable reception of information by subscribers. For the same purpose, in response to each byte of the received information and signal P.K, a request signal ЗпА of the next byte is issued from the subscriber.

0 The last RFA signal (to the last received fifth byte) means confirmation of receipt of this last byte.

In order to increase the reliability of the data transfer process for each signal P. Page K, the shaper 19 generates a time interval during which the arrival of signal Z.A. is expected Ee, if Zp.A signal is not received during this time interval, then from the output of the former 19

0, a status error signal is generated in the state register 7 with the subscriber. When a signal Zp.A arrives at a predetermined period of time or after a lapse of time, the former 19 is reset.

The 5 channel READ mode starts with the computer accessing the status register 7. For this, the computer sets the address to decoder 5 via line 22, which decodes it and generates a signal for block 6 (for a separate bit). Block 6 sends a signal to the state register 7 and to block 4. The state of register 7 is read by the computer via line 22 through block 3, after which the former 9 resets block 6. After the state of a certain bit, the computer register 7 learns about the device’s readiness to receive or transmit information. ..- ..

The computer learns about the need to read information transmitted to the subscriber by

0 interrupt signals set by the subscriber.

The interrupt signal from the subscriber arrives on one of the lines 23 through block 20.1 and block 15 (controlled by counter 13) to the block

5 14.

As a result, the subscriber who first set the interrupt signal forms his address (byte), which is received and written to block 1 through the block of receivers 20.2.

The transmission of each byte (one byte of the address and four bytes of data) t from the subscriber to block 21 is accompanied by strobe P. A, in response to which the signal Zp.K is generated from the output of one-shot 12 through block 21. This exchange of signals provides increased reliability of the data transfer process.

Shaper 18, which is triggered by each signal Pag. A received from the subscriber, and block 11, which monitors the oddness of each byte of information from the subscriber in the presence of an ACP check bit signal, serves the same purpose. An error signal from the output of block 11 is output to register 7.

Block 18 forms the time interval during which the arrival of the fifth signal Pag. A from the fifth output of the distributor 10 is expected. If during this time interval the fifth signal P. A does not arrive at the input of the distributor 10, then a signal about error exchanging with the subscriber. When the fifth signal Pg. A arrives at a predetermined period of time or after a certain time, the former 18 is reset.

The distributor 10 generates signals for block 1 to record each byte of information received from the subscriber through the block of receivers 20.2 to the inputs of block 1.

The synchronization unit 14, to the input 4 of which clock pulses are supplied from the generator 17, generates an output signal 1 from the output 1 for the computer through the block 3 along the line 22.

The computer, after processing the interrupt signal, detects the state of register 7 and then reads the information contained in block 1. according to the previously described procedure.

Claims (1)

 The claims A device for exchanging information between computers and subscribers, comprising a transceiver unit, a control signal receiver unit, a first allocator, a decoder, a memory register, a status register, a first receiver unit, a transmitter unit connected by input / output groups with device inputs / outputs for connecting to the inputs / outputs of the respective subscribers, the inputs / outputs of the transceiver unit, the information inputs of the decoder and the receiver unit of the control signals are connected to the inputs / outputs of the device for connecting to the computer data bus, to the computer address bus. to the control bus, respectively, the first group of inputs of the block the transceivers are connected to the group of outputs of the first distributor, the second group of inputs of the block of transceivers is connected to the group of outputs of the first block 5 of receivers, the first output of the block of receivers of control signals is connected to the synchronization input of the pengch register. the information inputs of which are connected to the outputs of the decoder, characterized in that, in order to increase the reliability of the data transfer process, the device comprises an error detection unit, a second distributor, an oddity control unit, a synchronization unit, a 5-pulse clock generator, two time delay generators, a counter, control bit shaper, control signal transmitters block, one-shot, multiplexer, pulse shaper, 0 second receiver unit, the second and third outputs of the receiver unit of the control signals connected to the first and second inputs of the transceiver unit, the third input of which is connected to the first output 5 of the memory register, the second output of which is connected to the clock input of the error detection unit and the input of the state register, the third and fourth outputs of the memory register are connected to the first and second 0 inputs of a block of control signal transmitters, the outputs of which are connected to the outputs of the device for connecting to a computer control bus, a group of inputs of a block of transmitters of control signals is connected to a group of outputs of the status register, the third input of a block of control signal transmitters is connected to the first output of the synchronization block, the second output which is connected to the reset inputs of the error detection block, counter, and the first and second distributors, the group of information inputs of the multiplexer is connected to the group of outputs of the second th receiver unit, a group of inputs of which is c uppoy 5 inputs of the device for connecting to the corresponding outputs of the interrupt request of the subscribers, the address inputs of the multiplexer are connected to the digital outputs of the counter, the first output of the transmitter unit 0 control signals are also connected via a pulse shaper to a memory register reset input, a group of outputs of a transceiver unit is connected to a group of information inputs of a detection unit 5 errors, the driver of the control bit and the block of transmitters, the first input of which is connected to the output of the former el of the control bit, the third group of inputs of the block of transceivers is connected to the outputs of the second distributor. (IF) the output of which is connected to the reset input of the first shaper of the time interval, the resolution input of which is connected to the first output of the receiver block with the clock input of the second pulse distributor, with the synchronization input of the oddity control unit and through the one-shot with the control input of the transmitter block, the second output of the second receiver block and the group of outputs of the first block of receivers is connected to the input of the sign of parity and the group of information inputs of the block of oddities, respectively, the output of which is connected to the fourth information input of the status register, the third information input of which is connected to the error flag output of the error detection unit, the fourth and fifth information inputs of the status register are connected to the outputs of the first and second time interval shapers, respectively, the status register reset input is connected with the third output of the synchronization unit, the fourth output of which is connected to the synchronization input of the first pulse distributor, the fifth output of the synchronization unit is connected to the counter input of the counter a, the sixth and seventh outputs of the synchronization unit are connected to the second and third inputs of the transmitter unit, the eighth output of the synchronization unit is connected to the enable input of the second driver of time intervals and the fourth input of the transmitter unit, the start input of the device is connected to the start input of the synchronization unit, the first input of the operation mode setting the synchronization unit is connected to the output of the multiplexer, the second input of setting the operating mode of the synchronization unit is connected to the third output of the second receiver unit and the reset input of the second ormirovatel timeslots. Kr about- Ј shits g