JPH05236027A - Input signal interruption detection system - Google Patents

Abstract

PURPOSE:To detect signal interruption with high reliability by using a counter so as to count number of consecutive 0s in reception data and using a comparator to discriminate interruption of an input signal when the number of consecutive 0s exceeds a prescribed value. CONSTITUTION:A reception signal subjected to sampling and holding based on a transmission clock SCLK by a sampling circuit 1 is latched at a leading timing of the transmission clock. A counter 2 is loaded with an inverting output and the clock SCLK from the circuit 1 and counts up the reception signal when the level is 0, and resets itself when the level of the reception signal is 1. Then, a gate circuit 3a outputs a level 0 when the count output indicates number of consecutive 0s less than a prescribed value, that is, each output other than a QD output from the counter 2 is not 1. Then, the output from the circuit 3a is latched by a latch circuit 5, and then, an input signal interruption detection signal is outputted. Thus, the circuit is simplified and the cost is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input signal loss detection method suitable for detecting an input signal loss (LOS) performed by a PCM line terminal (DT) in an electronic exchange or the like.

[0002]

2. Description of the Related Art FIG. 5 shows an exchange, which has an exchange (call path) 21 through which a PCM circuit terminating device (DT) 20 'is provided. Terminal 24 is connected. In addition, the exchange 21
It has a main controller 22 and a main memory 23.

The PCM circuit terminating device 20 'has a function of receiving an input PCM signal received in a bipolar manner, outputting reception data of a unipolar signal and a reception clock therefrom, and detecting a disconnection of the input signal. There is. Therefore, paying attention to the above-mentioned function, this PCM circuit terminating device 20 'has a bipolar / unipolar converter 11, a clock extraction circuit 12, Analog filter 1
3. A level detector 14 as an input signal disconnection detection circuit is provided.

Then, the bipolar / unipolar converter 1
1 and the clock extraction circuit 12 are connected to an elastic store memory (not shown) for speed conversion. Here, the bipolar / unipolar converter 11 converts the received bipolar signal into a unipolar signal and outputs it as received data. Clock extraction circuit 1
Reference numeral 2 is for extracting a clock from the input PCM signal and outputting it as a reception clock, and a tank circuit or the like is used.

The analog filter 13 extracts a specific frequency component of the received signal with an analog filter. The level detector 14 monitors the output from the analog filter 13 and the level becomes a value below the threshold. If the input signal is off, a signal indicating that the input signal is disconnected is output. Input signal loss (LOS) means PC
It is one of the M line faults, and it means that the receiving end cannot receive the signal and the receiving clock cannot be extracted.

With such a configuration, as a method for detecting the input signal loss, a specific frequency component of the received signal is extracted by the analog filter 13, and the level detector 1 is further used.
4, it is assumed that the output of the analog filter 13 is monitored and the input signal disconnection is detected when the level becomes a value below the threshold.

[0007]

However, in such a conventional input signal disconnection detection method, since the circuit configuration is made up of analog elements, high accuracy is required for the filter and the like to be used, and adjustment work and the like are also required. Will be needed. Furthermore,
It is difficult to accurately maintain the detection condition for disconnection of the input signal due to changes in characteristics due to aging of parts and the like.

Further, since the input signal disconnection detection condition is determined by the number of consecutive 0s in the received signal, it is difficult to accurately realize the condition in an analog circuit. The present invention was devised in view of such problems, and it significantly reduces the need for adjustment, greatly reduces the effect of aging, and accurately and inexpensively even if the precision of parts is low. Another object of the present invention is to provide an input signal loss detection method capable of realizing input signal loss detection.

[0009]

FIG. 1 is a block diagram of the principle of the present invention. In FIG. 1, reference numeral 10 denotes an input signal loss detection circuit. The input signal loss detection circuit 10 includes a sampling circuit 1, a counter 2, and a counter 2. It is provided with a comparator 3. Here, the sampling circuit 1 samples the received data, which is an input signal, with a clock irrelevant to the received clock.

A clock used in the transmitting section can be used as a clock unrelated to the reception clock. The counter 2 receives the output of the sampling circuit 1 and counts the number of consecutive 0s in the received data. The comparator 3 receives the count value of the counter 2 and the number of 0s exceeds a predetermined value. And a signal indicating that the input signal is disconnected.

The counter 2 can be configured to output a count value with a plurality of bits, and the comparator 3 can be configured as a multi-input AND gate that receives the multi-bit output of the counter 2. It is also possible to provide a latch circuit that holds the comparison determination result from the comparator 3.

[0012]

In the above-described input signal disconnection detection system of the present invention, as shown in FIG.
As shown in FIG. 3, the sampling circuit 1 samples the received data, which is an input signal, at a clock irrelevant to the received clock (for example, a clock used in the transmission unit), and then the counter 2 continuously outputs 0s in the received data.
Count the number of Then, the result of this counting (plural-bit output) is compared with a predetermined value by the comparator 3 (for example, plural-input AND gate).

When a latch circuit is provided, the comparison result from the comparator 3 is held by this latch circuit.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. 2 is a block diagram showing an embodiment of the present invention. In FIG. 2, reference numeral 20 denotes a PCM circuit terminating device,
This device 20 is used in place of the conventional PCM circuit termination device 20 'shown in FIG.

The PCM circuit termination device 20 is also
Similar to the conventional one, it has the functions of bipolar / unipolar conversion of the received signal (received data), extraction of the received clock, and detection of input signal loss (LOS) by the transmitted clock. Focusing on the above functions, this PCM circuit termination device 20
As shown in FIG. 5, the input PCM signal (bipolar signal) reception side is provided with a bipolar / unipolar converter 11, a clock extraction circuit (CLK EXT) 12, and an input signal loss detection circuit (LOS detection circuit) 10. There is.

The bipolar / unipolar converter 11
The output side of the clock extraction circuit 12 is connected to an elastic store memory (not shown) for speed conversion as in the conventional case. Further, the bipolar / unipolar converter 11 and the clock extraction circuit 12 are the same as those in the conventional example, and receive the input PCM signal sent in bipolar, and receive the received data of the unipolar signal and the received clock. Is output.

The input signal disconnection detection circuit 10 includes a bipolar /
A clock irrelevant to the received signal after unipolar conversion, for example, a clock used in the transmitter is diverted as the input signal disconnection detection monitoring clock, whereby the received signal is monitored to count the length of 0 consecutive signals. However, the input signal disconnection is detected. Since the PCM circuit terminating device 20 generally contains a transmitter and a receiver, it is possible to obtain a transmission clock irrelevant to the received signal.

The PCM circuit terminating device 20 having such a configuration
Thus, the received data from the bipolar / unipolar converter 11 is sent to the elastic store memory and the input signal loss detection circuit 10. Then, the reception clock of the clock extraction circuit 12 is also output to the elastic store memory. Further, a clock (transmission clock) used in the transmission section of the PCM circuit termination device 20 and irrelevant to the received signal after the bipolar / unipolar conversion is the input signal disconnection detection monitoring clock supplied to the input signal disconnection detection circuit 10. Is diverted as.

In response to this transmission clock, the input signal disconnection detection circuit 10 counts the length of 0 consecutive signals in the received signal and monitors the received signal to detect the input signal disconnection. By the way, the input signal loss detection circuit 10
3, is provided with a sampling circuit 1, a counter 2, a gate circuit 3a, a latch circuit 5 and the like.

Here, the sampling circuit 1 is composed of a flip-flop (FF), and has a clock SCL from the transmission section described above, which is unrelated to the reception clock.
By using K as the input signal disconnection detection monitoring clock, the received signal RDATA that is the input signal is sampled. That is, the sampling circuit 1 samples and holds the reception signal RDATA by the transmission clock SCLK. A counter 2 and a latch circuit 5 are connected to each output side of the sampling circuit 1.

The counter 2 is connected so as to receive the transmission clock through the inverting circuit 4, and the counter 2 is further connected.
The count output (4 bit output) of is input to the gate circuit 3a. Then, the counter 2 counts the number of consecutive 0's in the received signal (output from the sampling circuit 1) by the transmission clock inverted by the inverting circuit 4, and further inputs to the load end thereof. The sampling circuit inverted output is incremented by 0 and reset by 1. The counter 2 has an appropriate load value (in this example, twice the number of consecutive 0s which is a condition for detecting an input signal loss).
Is set to.

When the count output having the number information of 0 of the counter 2 exceeds a predetermined value (8 in this example), the gate circuit 3a determines that the input signal is disconnected, and outputs a signal indicating that to the latch circuit 5a. Input to the set end of. Therefore, the gate circuit 3a constitutes a comparator which outputs a signal indicating that the input signal is disconnected when the number of 0s counted by the counter 2 exceeds a predetermined value, and further receives a plurality of bits output from the counter 2. It is configured as a multi-input AND gate.

The latch circuit 5 receives the input signal disconnection determination signal from the gate circuit 3a at its set end and the non-inverted output of the sampling circuit 1 at its reset end to release the input signal disconnection state. And, the set contents are reset. As a result, the latch circuit 5 can hold the comparison / judgment result from the gate circuit 3a. A flip-flop is used as the latch circuit 5.

With the above configuration, the reception signal RDATA output from the bipolar / unipolar converter 11 [FIG.
(See (b)], the reception clock RCLK [see FIG.
(See (a)], which is irrelevant to
(See (c)] is used as the input signal disconnection detection and monitoring clock, and sampling is performed by this. By the way, the transmission clock at this time is twice the frequency of the reception clock RCLK.

Since the reception signal sampled and held by the sampling circuit 1 based on the transmission clock SCLK is latched at the rising timing of the transmission clock, the non-inverted output of the sampling circuit 1 is shown in FIG.
As shown in FIG. 4D, the inverted output of the sampling circuit 1 becomes as shown in FIG. Furthermore, the sampling circuit 1
The counter 2 counts up when the received signal is 0 by loading with the inverted output (see FIG. 4 (e)) and the transmission clock SCLK, and resets when it is 1 (FIG. 4 (f). )reference〕.

The gate circuit 3a determines that the counter output value is 0 or less consecutively, that is, the counter 2
0 when each output other than QD output does not become 1.
The level is output, and when all the outputs other than the QD output from the counter 2 become 1, the level 1 is output [Fig.
(See (g)]. After that, the output from the gate circuit 3a is latched by the latch circuit 5. As a result, FIG.
The input signal disconnection detection signal as shown in (h) is output.

After the latch circuit 5 is set, the received data RDAT returned to the 1 level by the sampling circuit 1.
When A is sampled, it is reset, so that the input signal disconnection detection signal becomes 0 level to notify that the input signal disconnection state has been released [see FIG. 4 (h)]. Further, the transmission clock SCLK is, as seen in this example,
Although it is necessary to use a clock having a frequency higher than the reception clock RCLK, even if the clock of the transmission unit is not used as a clock for sampling the reception data, the reception clock is not affected and the frequency of the reception clock is higher than that of the reception clock. Any clock may be used as long as it is a clock.

As described above, by sampling the received data, which is the input signal, with a clock irrelevant to the received clock, when the number of consecutive 0's in the received signal exceeds a predetermined value, it is determined that the input signal is disconnected. By doing so, there is no need to use parts with high precision and adjustment, and
The effect of aging can be reduced. as a result,
Highly accurate detection of input signal disconnection can be realized with a very simple circuit, which greatly contributes to cost.

[0029]

As described in detail above, according to the input signal loss detection method of the present invention, sampling for sampling received data as an input signal at a clock (clock used in the transmission section) unrelated to the received clock. A circuit, a counter for receiving the output of the sampling circuit and counting the number of consecutive 0s in the reception data (for example, a counter configured to output a count value with a plurality of bits is used), and the counter. When the number of 0's exceeds a predetermined value in response to the count value of 0, a comparator which outputs a signal indicating that the input signal is disconnected (for example, a comparator having a plurality of input and gates for receiving a plurality of bits of the counter) is provided. , In the sampling circuit, by sampling the received data as an input signal with a clock irrelevant to the received clock, The number of consecutive 0's in the received data is counted, and when the number of 0's exceeds a predetermined value, the comparator judges that the input signal is disconnected, so that a very simple circuit can be used for highly accurate input. There is an advantage that signal loss detection can be realized and cost reduction can also be realized.

By providing a latch circuit,
It is possible to hold the comparison judgment result from the comparator,
This has the advantage of facilitating the handling of data when performing data processing thereafter.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a block diagram showing details of an input signal disconnection detection circuit according to an embodiment of the present invention.

FIG. 4 is a timing chart illustrating an operation in one embodiment of the present invention.

FIG. 5 is a block diagram showing a switching center in a telephone network.

FIG. 6 is a block diagram showing details of a PCM circuit termination device used in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sampling circuit 2 Counter 3 Comparator 3a Gate circuit 4 Inversion circuit 5 Latch circuit 10 Input signal disconnection detection unit 11 Bipolar / unipolar converter 12 Clock extraction circuit 13 Analog filter 14 Level detector 20, 20 'PCM circuit terminator 21 Exchanger 22 main control device 23 main storage device 24 terminal

Claims (5)

[Claims] 1. The number of consecutive 0s in the received data is counted by sampling the received data, which is an input signal, with a clock irrelevant to the received clock, and when the number of 0s exceeds a predetermined value. An input signal loss detection method characterized by determining that the input signal is lost. 2. A sampling circuit (1) for sampling received data, which is an input signal, with a clock irrelevant to the received clock, and the number of consecutive 0's in the received data when receiving the output of the sampling circuit (1). And a comparator (3) which receives the count value of the counter (2) and outputs a signal indicating that the input signal is disconnected when the number of 0 exceeds a predetermined value. In the sampling circuit (1), the received data as an input signal is sampled at a clock irrelevant to the received clock, so that the counter (2) counts the number of consecutive 0's in the received data. An input signal disconnection detection method, wherein when the number of 0 exceeds a predetermined value, the comparator (3) determines that the input signal is disconnected. 3. The input signal loss detection method according to claim 1, wherein a clock used in a transmission section is used as a clock irrelevant to the reception clock. 4. The multi-input AND gate, wherein the counter (2) is configured to output a count value with a plurality of bits, and the comparator (3) receives a multi-bit output of the counter (2). The input signal disconnection detection method according to claim 2, wherein the input signal disconnection detection method is configured as follows. 5. The input signal loss detection method according to claim 2, further comprising a latch circuit for holding a comparison determination result from the comparator (3).