JPS63284954A - Break level detection circuit - Google Patents

Abstract

PURPOSE:To respond to a various kinds of baud rates in an asynchronous transmission system flexibly, by providing a criterion value generating part which generates plural reference values to decide a break level. CONSTITUTION:A central processing unit 40 sends prescribed data and the write pulse of the data to the criterion value generating part 50c corresponding to the status of a data communication system. Then, the generating part 50c generates the plural reference values to decide the break level. And when a break time is measured, a reference break level time sent from the generating part 50c in advance is loaded on a counter part 50b. The counter past 50b detects a carrier at a time when reception data changes from a high level to a low level according to a loaded value, and outputs a break level pulse.

Description

[Detailed Description of the Invention] (Summary) This is a break level detection circuit in an asynchronous communication system, and when detecting a break level, the number of bits set in advance for the break level time to be measured is set as one character, and transmission data is detected. By configuring the counter to load the number of characters according to the configuration contents, it is possible to realize a circuit that can flexibly determine the break level without being affected by the baud rate of the transmitted data with a simple configuration. It becomes possible.

[Industrial application field]

The present invention relates to a break level detection circuit in an asynchronous communication system.

For example, when transmitting data via a communication line between data terminal devices in remote locations or between a data terminal device and a host computer, a predetermined interface (for example, R5232C, etc.) is used to transmit data. It is being done.

In such data transmission, the speed at which data is transmitted and the transmission method (for example, serial transmission or parallel transmission)
In order to accurately transmit and receive data, various synchronization methods and the like are determined, and data transmission is optimally suited to the purpose.

The asynchronous transmission method is one such data transmission method, in which signals with the same period are not transmitted continuously, but signals with the same period are transmitted only between a certain group of bits. It is used in cases.

Further, this start-stop synchronization transmission method is a method of resynchronizing each bit group, and the bit groups usually consist of several bits to several tens of bits. Note that data transmission speeds that are usually medium or lower are widely used.

As for the code structure of the asynchronous transmission method, a start bit and a stop bit are added before and after a data bit to form a code, and the timing is determined for each code.

These synchronization detection functions for data transmitted with asynchronous synchronization and resetting functions when out-of-synchronization etc. are detected are used to perform modulation and demodulation of data transmitted and received via communication lines installed for data transmission, for example. installed in the modem.

Generally, as semiconductor technology advances, such devices tend to become more highly integrated and smaller. Further, there is a demand for a configuration that can be used regardless of the transmission speed of data to be transmitted (baud rate 1-) or the number of bits in one code. .

[Conventional technology]

FIG. 5 is a block diagram illustrating a conventional example, FIG. 6 is a diagram illustrating the configuration of asynchronous transmission data, and FIG. 7 is a diagram illustrating the configuration of a data communication system.

In this example, data is transmitted and received using the asynchronous transmission method, and FIG. 7 is a diagram showing an example of the device configuration of the data communication system when data is transmitted using the asynchronous transmission method.

The device configuration of this data communication system includes a data terminal device (which serves as a terminal device for the communication line (a) and also transmits and receives data via the communication line (a)).
DTE) 100, an encryption device 2200 that performs processing to maintain the confidentiality of data transmitted via the communication line (a), and a data terminal device when using the communication line (a) forming an analog transmission path. (DTE) 100 into an analog signal.

In addition, in FIG. 7, the data receiving the code RD, the code S
D is displayed as data to be transmitted. Furthermore, it is assumed that the synchronization detection function and break level detection function for data transmitted and received using the asynchronous transmission method are incorporated in the encryption device 200 or the modem 300 in FIG.

Note that the break level is determined by the data terminal equipment (DTE) 100 and the encryption device 200 or modem 3 as shown in FIG.
This command is used as an initial setting resetting command when starting over when setting a connection path for transmitting data to and from 00, and when the previous attempt to retain information fails.

That is, generally, a plurality of data terminal devices (DTI 100) are connected to the encryption device 200 or the modem 300.

Therefore, when accessing the encryption device 200 or modem 300 for data transmission, which data terminal device (
In order for the encryption device 200 or the modem 300 to identify whether the access is from the DTE 100, for example, IO information is first sent.

When the encryption device 200 or the modem 300 confirms this 10 information, it sends back a permission signal for permitting access for data transmission to the data terminal equipment (DTE) 100, and the data terminal equipment (DT
E) Wait for data transmission from 100.

At this time, if the permission signal cannot be confirmed within the specified time by the data terminal equipment (DTE) 100 due to the influence of noise, etc., the data terminal equipment (DTE) 100
A break level consisting of a "low" level with a predetermined bit length of 100i is sent to the encryption device 200 or the modem 300, and both are put into the initial setting state and the process starts again from sending the ID information.

FIG. 5 shows the configuration of a circuit for detecting such a break level and a circuit for detecting synchronization of data transmitted using the astop synchronization method.

The circuit configuration shown in Fig. 5 includes a falling detection circuit 1 that detects the falling edge of received data RD (digital data), and a falling detection pulse from the falling detection circuit 1 and a start bit that is detected from the received data RO. A clock generation circuit 3 generates various clocks for data detection using the start bit detection pulse from the start bit detection circuit 2;・A serial/parallel conversion circuit (hereinafter referred to as S/P conversion circuit) 4 that converts parallel data into parallel data, and a break level detection section 5 that detects a break level using the clock generated from the clock generation circuit 3 and the received data RD. It is equipped with:

Data transmitted using the asynchronous transmission method has a configuration as shown in FIG. 6(1).

Immediately, the fall from the "high" level to the "low" level is used as the start bit, and then the "high" level is set at a predetermined bit (set in the range of 5 to 9 bits, in this example, 8 bits) consecutively. The data bit is configured as a data bit, and the "high" level of several bits (1 to 2 bits) following the data bit is configured as a stop bit.

In this example, the start bit and data bit.

It is assumed that one data code (one character) up to the stop bit is composed of 10 bits.

On the other hand, the break level consists of several bits of "low" level as shown in FIG. This is an example in which the break level is set to the width of (usually several characters long to clearly distinguish it from the "low" level of data).

Note that since the break level is transmitted at the same baud rate as the data to be transmitted, the time width of the break level changes depending on the baud rate of the data.

The conventional break level detection section 5 is configured as shown in FIG.

That is, the received data RD input from the outside is synchronized with a predetermined clock (for example, the clock generated by the clock generation circuit 3 at a baud rate x 16) using a D-type flip-flop (hereinafter referred to as DF, F) 51. .

Next, the break level determination circuit 52 determines whether the received data RD is at the break level based on a reference value preset in hardware based on the length of the low level, and determines that the received data is at the break level. In this case, a break level detection signal (■) is sent out for initial setting of a circuit (not shown).

Note that the break level determination circuit 52 stores a predetermined break level determination reference value (“low” level time fpFA at a predetermined baud rate), and in this example, the reference value is: Baud rate shown in Figure 6 (2) x
This is the time width when 1 character is 10 bits at the time of 16.

As mentioned above, this break level is used as a reset command to reset each function of the data communication system, for example, when the asynchronous transmission data as shown in Figure 6 (1) becomes out of synchronization due to some abnormality. After initializing each function with this υ set command,
Preparations for data transmission will begin again.

[Problems to be Solved by the Invention] As described above, the break level determination reference value set in hardware is set to be compatible with one baud rate.

That is, since the break level determination reference value is set by hardware, for example, when 10 bits are used as one character, the "low-parameter length and time width" is fixed depending on the baud rate at that time.

Therefore, if the baud rate is changed, it is necessary to change the setting of the break level judgment reference value set in the break level judgment circuit 52, that is, to change the hardware.

As described above, the conventional example described above has a problem in that it cannot flexibly respond to various baud rates.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

The break level detection circuit of the present invention shown in FIG. 1 consists of data synchronization detection means 60. A central processing unit (hereinafter referred to as CPIJ) 40 that sends out predetermined data and write pulses of the data according to the break level detection unit 50 and the data communication system status.
It is configured with the following.

Furthermore, the break level detection unit 50 according to the present invention has a configuration including a data change point detection unit 50a that detects the change point of the rising/falling edge of received data, and an output from the change point detection unit 50a, and a set value thereof. and a counting unit 50b that performs counting at a predetermined clock, and generates a plurality of reference values for determining a break level to be used as a reset command to initialize the data communication system when an abnormality is detected during data transmission. The determination reference value generation unit 50c is configured to include a determination reference value generation unit 50c.

Note that the data synchronization detection means 6o having the same function as the circuits 1 to 4 explained in FIG.
).

[Effect]

When measuring and determining the break level time, the reference break level time sent from the determination reference value generation unit 50c is loaded into the counting unit 50b, and when the carry from the counting unit 5°b turns on, the break level is determined. By configuring it to do so, it becomes possible to detect the break level in a flexible and simple manner without being affected by the baud rate of the transmitted data.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 to 4.

FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a time chart in an embodiment of the present invention,
FIG. 4 shows diagrams explaining the break level determination criteria in the embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

In this embodiment, the data conversion point detection section 50a shown in FIG.
The determination reference value generation section 50c is composed of a register 56 and a logic operation circuit 57.

FIG. 2 shows an outline of the configuration of the break level detection section 50 according to the present invention. Received data l? output from F, F1a and D-F, F1a? Differentiation circuit 5 that detects rising/falling by differentiating D
4, a counter 55 that loads the break level judgment standard sent from the logic operation circuit 57 with the rising/falling detection signal XCPLS output from the differentiating circuit 54, and starts counting with the counter CK, and a break level sent from the CPU 40. Data regarding level judgment criteria DO~D7 (8 types of data are sent)
and a logic operation circuit 57 that performs a logical operation on a predetermined character length serving as a break level determination standard (that is, obtains the set value shown in FIG. 4) using the data Do-07 stored in the register 56. , the time when the counter 55 sends out a predetermined carry is the received data R.
An AND circuit that takes the AND condition of whether it is a pulse when D changes from a “high” level to a “low” level (see
(referred to as D) 58, and a register 59 that sets a flag of "1" when the output of the AND 58 is turned on.

From CPIJ40, 8 types of bit data DO~D7
It is assumed that the write pulse WPLS and the write pulse WPLS can be sent out based on a predetermined program.

When this bit data DO-07 is written to the register 56 and read out, this bit data DO~D7 is sent to the logic operation circuit 57, and depending on the contents of the bit data DO~D7, as shown in FIG. A break level determination reference value is calculated and sent to the data terminal of the counter 55.

Incidentally, FIG. 4 is a diagram showing break level determination reference values, and shows eight types of break level determination reference values and corresponding set values and count values of the counter 55.

For example, when the CPU 40 sends 7 bits to the logical operation circuit 57 via the register 56 depending on the content of the data received, the set value of the counter 55 is set to "F5F"', and the counted value at that time is "160°". “becomes.

This set value "F5F" is loaded by the rising/falling detection signal XCPLS from the differentiating circuit 54, and counting is started with the clock CK. For example, when the count value is "FFF" as shown in FIG. , carry ■ AND58
Send to.

AND58 takes the logical product condition of this carry, the received data RD, and the clock CK, and determines whether the carry is at the time when the received data RD changes from ``hyper'' to ``low'' (that is, all ``lower'' conditions). For example, it is sent out as a break level detection pulse, and the carry (2) when it changes from "low" to "hyper" is considered not to be at the break level and is stopped being sent out as a break level detection pulse.

When a break level detection pulse is sent from AND5B, the flag of the register 59 is set to "1", and a break level detection signal (2) is sent out for initial setting of a circuit (not shown).

That is, as shown in FIG.
The value corresponding to the baud rate obtained in step 7 is sent to the counter 55.
By loading it as a setting value, the counting time until the counter 55 reaches "'FFF" can be varied and set.

This adjusts the time during which the counter 55 sends the carry (2) to the AND 58. That is, the break level length is arbitrarily adjusted to correspond to the baud rate.

Note that each circuit of this embodiment (for example, the data synchronization detection means 6
0. As for the elements constituting the break level detection section 50, etc., the data synchronization detection means 60 is composed of a general-purpose LSi for digital communication;
The break level detection unit 5 is not equipped with that function.
It is assumed that 0 is composed of, for example, a logic IC or the like.

〔Effect of the invention〕

According to the present invention as described above, break levels can be determined and detected flexibly with respect to the baud rate of transmission data, most of which can be miniaturized using a general-purpose LSi, and moreover, the overall cost is lower. It is possible to realize a circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a time chart in an embodiment of the present invention, and FIG. 4 is a block diagram explaining the present invention in detail. 5 is a block diagram illustrating the conventional example; FIG. 6 is a diagram illustrating the configuration of asynchronous transmission data; FIG. 7 is a diagram illustrating the structure of asynchronous transmission data; Figures illustrating the configuration status are shown, respectively. In the figure, (2) is a fall detection circuit, 2 is a start bit detection circuit, 3 is a clock generation circuit, 4 is an S/P conversion circuit, 5.50 is a break level detection section, and 40 is a CPU. 50'a is a change point detection section, 50b is a counting section, 50c
51.53 is DF, F, 52 is a break level judgment circuit, 54 is a differentiation circuit, 55 is a counter, 56.
59 is a register, 57 is a logic operation circuit, 58 is A
'ND. 60 is a data synchronization detection means, 悌 40 Sakurai 411th Aro 1. FPJT 5th episode, 7th episode

Claims (1)

[Claims] A central processing unit (40) that controls operations within the device, a data synchronization detection means (60) that detects data synchronization when receiving and processing data using an asynchronous communication method, and a data transmission unit In a data communication device, the data communication device includes a break level detection unit (50) that detects a break level that occurs when an abnormality is detected in the break level detection unit (50).
0), a data change point detection section (50a) that detects the change point of the rising/falling edge of the received data, and the set value is loaded with the output from the change point detection section (50a), and a predetermined value is loaded. Counting unit that counts using a clock (
50b), and a determination reference value generation unit (50c) that generates a plurality of reference values for determining a break level to be used as a reset command to initialize the data communication system when an abnormality is detected during data transmission. and the change point detection section (50a
), when the break level consisting of preset arbitrary bits is detected, the determination reference value generation unit (5
An arbitrary judgment reference value generated in step 0c) is loaded as a setting value for the counting section (50b) using the detection output of the change point detection section (50a), and is sent out when the counted value reaches a predetermined counted value. 1. A break level detection circuit that determines that the break level is determined by confirming that a carry is on.