JPS62143534A - Signal waveform forming circuit - Google Patents

Signal waveform forming circuit

Info

Publication number
JPS62143534A
JPS62143534A JP60284835A JP28483585A JPS62143534A JP S62143534 A JPS62143534 A JP S62143534A JP 60284835 A JP60284835 A JP 60284835A JP 28483585 A JP28483585 A JP 28483585A JP S62143534 A JPS62143534 A JP S62143534A
Authority
JP
Japan
Prior art keywords
signal
clock signal
flip
outputted
multivibrator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60284835A
Other languages
Japanese (ja)
Inventor
Shunjiro Yui
俊二郎 由井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60284835A priority Critical patent/JPS62143534A/en
Publication of JPS62143534A publication Critical patent/JPS62143534A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To attain a stable waveform formation by providing a multi-vibrator which starts an oscillation synchronizing with a serial pulse after a regulated delay time, and a flip-flop circuit which obtains a code signal from a clock signal outputted from the multivibrator and an input signal. CONSTITUTION:A gate signal C having a time L regulated with a resistor R1 and a capacitor C1 is outputted from a multivibrator 11, and at the leading edge of the gate signal C, a clock signal D having a pulse width of T/2 (regulated with a resistor Rt and a capacitor Ct) is outputted with multivibrators 12 and 13. In other words, the oscillation is generated only during a gate time L. The clock signal D is inputted as the clock signal of a flip-flop circuit 14, and a distorted input signal A is inputted as an input data. A pulse E having a normal pulse width T (or integer fold of T) is outputted with the flip-flop circuit 14.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は光通信や一般ワイヤード通信等において、通信
用機器を多数接続した場合の通信用機器に内蔵されたシ
、遠距離通信を行う場合の信号中継器に内蔵されたりす
る信号波形成形回路に関するものである。
[Detailed Description of the Invention] Industrial Field of Application The present invention is applied to optical communications, general wired communications, etc., in which a large number of communication devices are connected, a built-in communication device, and a signal signal used in long-distance communication. This relates to a signal waveform shaping circuit that is built into a repeater.

従来の技術 従来、上記通信機器や(19号中継器においては、全信
号をコンピュータに入力し、再度、そのデータを回線上
に出力する方式や、第3図に示すよう2 ヘ一) な信号波形成形回路が用いられていた。すなわち、入力
信号のパルス巾の中に更に小さな巾のパルスが何個以上
入るかの判定により正式データとして検定し、データ成
形を行う方式である。この第3図においては、水晶発振
回路1および分周回路2によってカウント用パルスを作
成し、入力信号のゲートによりカウンタ3によってカウ
ントを行なう。カウンタ3が規定値になることによりデ
ータを入力信号として取り込み、規定信号数を取り込ん
だ所で、再度、分周回路2による規定周波数に従って形
成データとして出力する。なお、4はカウント設定部、
5はS/P変換器、6にl:P/S変換器である。
Conventional technology Conventionally, the above-mentioned communication equipment (in the case of No. 19 repeater, a method of inputting all signals to a computer and outputting the data again on the line, and a method of inputting all signals to a computer and outputting the data again on the line, as shown in Fig. 3), etc. A waveform shaping circuit was used. That is, this is a method in which the data is verified as formal data by determining how many or more pulses with a smaller width are included in the pulse width of the input signal, and the data is shaped. In FIG. 3, a counting pulse is created by a crystal oscillation circuit 1 and a frequency dividing circuit 2, and counting is performed by a counter 3 using a gate of an input signal. When the counter 3 reaches a specified value, data is taken in as an input signal, and when the specified number of signals have been taken in, the frequency dividing circuit 2 again outputs the data as forming data according to the specified frequency. In addition, 4 is the count setting section,
5 is an S/P converter, and 6 is an l:P/S converter.

発明が解決しようとする問題点 しかし、これらの方式は必らず伝搬時間に遅れが生ずる
。また、第3図に示す回路では、入力信号と発振クロッ
ク信号とのタイミングのずれ等が問題となる。さらに、
周波数に従って水晶発振回路および分周回路に影響を及
ぼし基本的な回路変更が必要となる場合がある。
Problems to be Solved by the Invention However, these methods inevitably cause a delay in propagation time. Further, in the circuit shown in FIG. 3, there is a problem such as timing deviation between the input signal and the oscillation clock signal. moreover,
Depending on the frequency, the crystal oscillator circuit and frequency divider circuit may be affected and basic circuit changes may be required.

3ページ 問題点を解決するためめ手段 上記問題点を解決するため、本発明は入力されるシリア
ルパルス符号に同期して一定遅延時間後に発振を開始す
るマルチバイブレータと、このマルチバイブレータから
出力されるクロック信号と入力信号により符号信号を得
るフリツプフロツプ回路を備えてなるものである。
Page 3 Means for Solving the Problems In order to solve the above problems, the present invention provides a multivibrator that starts oscillating after a certain delay time in synchronization with an input serial pulse code, and an output signal from the multivibrator. It comprises a flip-flop circuit that obtains a code signal from a clock signal and an input signal.

作  用 発振回路としてマルチバイブレータを使用し、信号と波
形成形に使用するクロック信号を入力信号と完全に同期
をとり、フリップフロップ回路により波形を成形する。
A multivibrator is used as an oscillator circuit, the clock signal used for signal and waveform shaping is completely synchronized with the input signal, and the waveform is shaped by a flip-flop circuit.

実施例 以下、本発明の実施例について第1図、第2図を参照し
て説明する。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 1 and 2.

第1図、第2図において、11はマルチバイブレータで
あり、抵抗R1とコンデンサC1で定まる時間りのゲー
ト信号(ハ)が出力される。このゲート信号(ハ)の立
下りで、マルチバイブレータ12゜13によりパルス巾
T/2(抵抗R4、コンデンサCtにより定寸る)のク
ロック信号に)が出力される。すなわち、ゲート時間り
の間だけ発振することになる。このクロック信号に)を
フリップフロップ回路14のクロック信号として入力し
、入力データとして歪んだ入力信号(イ)を入力する。
In FIGS. 1 and 2, 11 is a multivibrator, which outputs a gate signal (c) at a time determined by a resistor R1 and a capacitor C1. At the fall of this gate signal (c), a clock signal with a pulse width of T/2 (determined by the resistor R4 and the capacitor Ct) is outputted by the multivibrator 12-13. In other words, it oscillates only during the gate time. This clock signal) is inputted as a clock signal of the flip-flop circuit 14, and the distorted input signal (A) is inputted as input data.

このフリップフロップ回路14により正常なパルス巾T
(またはTの整数倍)のパルス(ホ)が出力される。
This flip-flop circuit 14 allows the normal pulse width T
(or an integral multiple of T) pulses (e) are output.

すなわち、成形さt′I−/こ信号が111力される。That is, the shaped t'I-/this signal is output at 111.

発明の効果 以上のように本発明に、1:れげ、回路構成が簡単であ
シ、かつ、クロック信号と入力信号の同期がとられ、安
定した波形成形が行われる。また、いかなる周波数に対
しても一部の抵抗とコンデンサの値を調整するだけで安
定したクロック信号がイUられるため、回路修正の必要
がない。さらに、データの構成による修正も、一部の抵
抗とコンデンサの値によりいかなるゲート巾もとれるた
め、自由に行える。
Advantages of the Invention As described above, the present invention has the following advantages: 1: The circuit configuration is simple, and the clock signal and input signal are synchronized, resulting in stable waveform shaping. Furthermore, since a stable clock signal can be generated by simply adjusting the values of some resistors and capacitors for any frequency, there is no need for circuit modification. Furthermore, modification by data configuration can be freely performed because any gate width can be obtained by changing the values of some resistors and capacitors.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す信号波形成形5ページ 回路の回路図、第2図は同回路の各部の信号波形図、第
3図は従来の信号波形成形回路の回路図である。 11.12.13・・・・マルチバイブレータ、14・
・・・・フリップフロップ回路。
Fig. 1 is a circuit diagram of a five-page signal waveform shaping circuit showing an embodiment of the present invention, Fig. 2 is a signal waveform diagram of each part of the circuit, and Fig. 3 is a circuit diagram of a conventional signal waveform shaping circuit. . 11.12.13... Multivibrator, 14.
...Flip-flop circuit.

Claims (1)

【特許請求の範囲】[Claims] 入力されるシリアルパルス符号信号に同期して一定遅延
時間後に発振を開始するマルチバイブレータと、このマ
ルチバイブレータから出力されるクロック信号と入力信
号により符号信号を得るフリップフロップ回路よりなる
信号波形成形回路。
A signal waveform shaping circuit consisting of a multivibrator that starts oscillating after a certain delay time in synchronization with an input serial pulse code signal, and a flip-flop circuit that obtains a code signal from the clock signal output from the multivibrator and the input signal.
JP60284835A 1985-12-18 1985-12-18 Signal waveform forming circuit Pending JPS62143534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60284835A JPS62143534A (en) 1985-12-18 1985-12-18 Signal waveform forming circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60284835A JPS62143534A (en) 1985-12-18 1985-12-18 Signal waveform forming circuit

Publications (1)

Publication Number Publication Date
JPS62143534A true JPS62143534A (en) 1987-06-26

Family

ID=17683626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60284835A Pending JPS62143534A (en) 1985-12-18 1985-12-18 Signal waveform forming circuit

Country Status (1)

Country Link
JP (1) JPS62143534A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03101432A (en) * 1989-09-14 1991-04-26 Nec Corp Data reception circuit
JP2006025142A (en) * 2004-07-07 2006-01-26 Audio Technica Corp Signal transmission apparatus for digital audio

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03101432A (en) * 1989-09-14 1991-04-26 Nec Corp Data reception circuit
JP2006025142A (en) * 2004-07-07 2006-01-26 Audio Technica Corp Signal transmission apparatus for digital audio

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