JPS6151456B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for synchronizing clock pulses for transmitting data and control signals between a main unit and a telephone in a button telephone apparatus using time division control.

Conventional button telephone devices use cables with multiple core wires to connect the main device and the telephone. However, in recent years, as systems have become larger and more multifunctional, materials and labor costs have also tended to increase, leading to an increase in system costs. Therefore, taking measures to reduce the number of cable core wires is an effective means for reducing costs.

To achieve this, a method has conventionally been used in which control signals are time-division multiplexed between the main device and the telephone. A source (clock, etc.) is required. Conventionally, one signal source was used in the main device.
There are two methods: one is to provide a dedicated channel to the telephone, and the other is to superimpose data on the data channel and send it from the main device, and the telephone separates only the clock from that signal. Of these, the former is a special method. The latter method had the disadvantage of complicating the equipment.

In order to solve these drawbacks, the present invention has independent signal sources with high and low repetition frequencies for the main device and the telephone, respectively, and divides the output of one of the signal sources with a high repetition frequency using a frequency dividing circuit. By configuring the frequency dividing circuit to be approximately equal to the repetition frequency of the output of the other signal source, and by configuring the frequency dividing circuit to be activated by the clock pulse of the other output, the clock pulse of each output of both The present invention provides a synchronization method for a key telephone device that enables time-division transmission of data and control signals by performing synchronization.

The present invention will be explained in detail below using the drawings.

FIG. 1 shows an embodiment of the present invention, 1, 27,
82 is a counter, 2 is a clock pulse generator that generates a clock pulse CP with a low repetition frequency, 81 is a clock pulse generator that generates a clock pulse CP' with a high repetition frequency, 4 and 28 are various timings according to the count value of the counter 1 or 27. Decoder for generating pulses, 83 is an AND gate, 84, 4
0 is flip-flop, 85, 86, 88, 89
is the inverter, 32 is the output T′ ₂ of the decoder 28,
. . . An OR gate whose input is T′ _o , and 33 is the contact point of the electric key.

In the embodiment shown in FIG. 1, the telephone side receives clock pulses.
The repetition frequency of CP' is divided by a counter 82 and applied to the counter 27, and the counting timing pulse CP of the counter 1 mounted in the main device and the counting of the counter 27 mounted in the telephone are configured. Each time-division pulse train, such as a decoder 28, is configured to be synchronized with a timing pulse, thereby sending each time-division pulse train from the telephone to the main unit.
The T' ₂ pulse of the output of the decoder 4 and the T' ₂ pulse of the output of the decoder 4 are generated at the same synchronous timing with a delay within a certain time.

In the operation of the circuit shown in FIG. 1, the counter 1 is driven by the first clock pulse CP which is the output of the first clock pulse generator 2, and the first clock pulse CP is applied to the output side of the decoder 4 connected to the output of the counter 1. Obtain pulses of synchronous pulse train T ₁ , . . . T _o . Among them, the pulse of _T1 is applied to the set terminal S of the flip-flop 84 via the first transmission means consisting of the route [inverter 88→inverter 85],
Set it. Next, by setting the flip-flop 84, the AND gate 83 is opened and the second
The second clock pulse CP' from the clock pulse generator 81 is counted by the counter 82, and its carry pulse becomes the counting pulse of the counter 27, and is counted by the decoder 28 connected to its output.
A second synchronous pulse train of T' ₁ , T' ₂ , . . . T' _o is obtained. Further, when the counter 27 completes the required count, for example, full scale count, the decoder 2 at that time
The output _T'F of 8 resets the flip-flop 84, which resets the counter 82 and the counter 27. Thereafter, the above operation is repeated again.

Here, if the flip-flop 84 is in the set state without the synchronizing pulse _T1 , the counter 27 counts according to the above operation, a pulse _T'F is generated, the flip-flop 84 is reset, and then a pulse This state is maintained until _T1 arrives at the set terminal S.

The above operation will be explained using the time chart shown in FIG. Here, CP' is an output clock pulse train having a high repetition frequency obtained from the clock pulse generator 81, and consists of a four-stage binary counter to count this and divide the repetition frequency into 1/16. 1 stage 2 stages 3 stages 4 of the counter 82
The respective slip outputs of the stages are expressed as C′ ₁ , C′ 2 , C′ ₂ ,
Shown in C′ ₃ and C′ ₄ . In order to clarify the relationship with the following signals, the pulse train of C' ₄ is shown in 2 with its time compressed as shown by the dotted line. That is, it is 1/16 of the repetition period _tcp of the repetition period _t'cp of CP'.
Next, when a synchronization pulse (this is caused by the output signal _T1 of the decoder 4 and shown in FIG. 2) arrives from the main device, the flip-flop 84 is set as shown in FIG. 2, and the AND gate 83 is opened. The counter 82 is driven by CP', the counter 27 also starts counting, and the output of the decoder 28 at this time
T' ₁ , T' ₂ , . . . are shown in 5 of Fig. 2.

Next, the output signal T' ₂ of the decoder 28 obtained in the above operation is sent to the flip-flop via the route [T' ₂ → contact 33 → OR gate 32 → inverter 86 → inverter 89] by connecting the contact of the electric key 33. 40 input terminals. Here, the flip-flop 40 is a D-type flip-flop, and is set at the rising edge of its gate pulse CP. That is, T'2 of 5 in FIG. ₂ is applied as an input signal to the flip-flop 40, and its gate is triggered by CP of FIG. 2 to obtain the output shown in FIG. 7. As a result, the output signal T ₂ of the decoder 4 and the incoming signal T' ₂ from the telephone set are completely synchronized at the output of the flip-flop 40, and are used, for example, as information on the telephone key 33 from the telephone set to control the main unit. Here, in order to ensure the operation of the flip-flop 40, the timing pulses of T' ₂ and CP include a timing pulse of CP near the center of the pulse width of T' ₂ , as shown at 3 and 6 in FIG. It is determined that the rising edge of the pulse will occur.

Pulse trains other than T ₂ and T' ₂ are also synchronized and used for transmitting the corresponding target data or control signals, but their detailed representation is omitted in FIG.

Note that the repetition period of the clock pulse CP of the clock pulse generator 2 and the clock pulse generator 8
The repetition periods of the clock pulses CP' of 1 are selected in a fixed relationship, that is, the periods of the clock pulses CP are selected to be larger than the period of the clock pulses CP' by the frequency division ratio of the counter 82, and those periods are highly accurate. Set.

For example, if we assume that n of T _o is 10, then T ₁ ...
... _T10 . Here, assuming that there is an error Δ between the period of CP and the period of CP', the time A during which the counter 1 counts the full scale by CP is 10t _cp , where t _cp is the period of CP. Similarly, if the period of CP' is t' _cp , the time B for the counter 27 to count the full scale is 10t' _cp . Also, from the above assumption, t _cp = t' _cp ±Δ, so the error between A and B is A - B = 10t _cp - 10t' _cp = 10 (t' _cp + Δ) -
10t′ _cp = ±10Δ.

Next, in order to receive the signals T' ₁ ...T ₁₀ from the telephone at the flip-flop 40 of the main device, as mentioned above, if there is no error between CP and CP', then T' ₁ ...
T ₁₀ (or T ₁ ...T ₁₀ , in this case T' ₁ to T' ₁₀
It is desirable that the input to the flip-flop 40 be near the center of each pulse width (the pulse widths from T _{1 to T 10 are} the same), but if there is the error mentioned above, As the count progresses, the input position to the flip-flop 40 changes from the center to ±
The deviation is Δ, ±2Δ, ...±10Δ. As a result, T′ ₁₀
, there will be a deviation of ±10Δ, which is
When the pulse width of _T'10 becomes 1/2 or more, the pulse of _T'10 cannot be input to the flip-flop 40.

Also, the clock pulse of the clock pulse generator 2
Due to the phase difference between CP and the clock pulse CP' of the clock pulse generator 81, T ₁ ...T _o and T' ₁ ...T' _o
An error equal to the maximum frequency division ratio of the counter 82 occurs between the two, but this can be reduced by setting the frequency division ratio large.

Here, there are the following two reasons for causing the above error. The first error is an error in the repetition period of the output pulses of clock pulse generator 2 and clock pulse generator 81.

The second error is an error due to a synchronization difference between the clock pulse generator 2 and the clock pulse generator 81, which are asynchronous oscillators. Since the start of the counter 27 is delayed by this synchronization difference, T' ₁ is shifted with respect to T ₁ by that amount.

In the present invention, a counter 82 is inserted in order to reduce this shift. As described above, it is necessary to set the errors of the clock pulse generators 21 and 81 and the counter 82 so that the sum of the first and second errors becomes 1/2 of the pulse width of _T'10 . These can be easily achieved by using a crystal oscillation circuit as the oscillation circuit of the clock pulse generator and by using a four-stage binary counter as the counter 82.

Note that the pulse T ₁ is also applied to the flip-flop 40, but unnecessary operations due to this pulse T ₁ can be prevented by known means such as arranging a gate circuit at the input or output of the flip-flop 40. . In this case, when a gate circuit is inserted at the input of the flip-flop 40, it is blocked by T ₁ , and when a gate circuit is inserted at the output of the flip-flop 40, it is blocked by T ₂ to prevent the read output from being output. The gate circuit can be controlled to prevent this.

As explained above, the present invention provides a simple and stable means for synchronizing the control signal and data transmission between the main device and the telephone, which has been a problem due to the reduction in the number of cable cores in conventional key telephone devices. Since data and timing signals can be transmitted in the same circuit, the circuit becomes simpler, and the effects on realizing a button telephone device using time-sharing control include miniaturization, cost reduction, and quality improvement. big.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a time chart for explaining the operation of the embodiment shown in FIG.

Claims (1)

[Scope of Claims] 1. A button telephone device that time-divisionally transmits control signals between a main device and a telephone, including a first clock pulse generator for generating a first clock pulse train in the main device, and a first clock pulse generator for generating a first clock pulse train; a first synchronization signal generation circuit that generates a first synchronization pulse train synchronized at a predetermined timing synchronized with the first clock pulse train; and a transmission means for transmitting the synchronization pulse train to the telephone; a second clock pulse generator within the telephone for generating a second clock pulse train having a period shorter than the period of the first clock pulse train; and a second clock pulse generator for counting pulses of the second clock pulse train. a frequency dividing circuit, a starting means for activating the frequency dividing circuit in response to the first synchronizing pulse train, and a second synchronizing circuit for generating at least one second synchronizing pulse train synchronized with the output pulse of the frequency dividing circuit. Equipped with a signal generation circuit,
The frequency division ratio of the frequency divider circuit is set so that the output cycle of the frequency divider circuit matches the cycle of the first clock pulse train, and the first synchronization pulse train and the second synchronization pulse train are synchronized. A synchronization method for a button telephone device, characterized in that it is configured as follows. 2. The activation means includes a flip-flop circuit that is set in response to the first synchronizing pulse transmitted by the transmission means and reset in response to a pulse obtained by further dividing the output pulse of the frequency dividing circuit. A synchronization method for a button telephone device according to claim 1, characterized in that: