SU621113A1 - Phase synchronization monitor - Google Patents

Description

(54) DEVICE OF PHASE SYNCHRONIZATION

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The designation relates to communications and can be used in the equipment of data transmission systems.

It is known a loop synchronization device in a discrete communication canal, containing a frequency divider, cell outputs of which are connected to clock generator inputs, marker generator group, the output of which is connected through AND elements to corresponding accumulators, gate drivers, through which the outputs of each cell of divider are connected to the second inputs of the corresponding elements AND, as well as the maximum allocation blocks, through which the outputs on the hoppers are connected to the additional inputs of the clock sync signal i.

The closest phase synchronization device to the invention contains a series-connected local oscillator and a delay line, the outputs of which are connected to the first inputs of the coincidence unit, to the second inputs of which is under-. The corresponding outputs of the memory block are turned on. And the outputs of the coincidence block are connected to the corresponding inputs of the L2 assembly block.

However, the known devices spend considerable time on entering into synchronism and are not operational at a frequency of the phasing signal that is a factor of several times lower than the frequency of the local oscillator.

The purpose of the invention is to reduce the time of entry into synchronism and ensure the operation of the device at frequencies of the lower signal, less than the frequency of the local oscillator by a factor of several times.

For this purpose, a phase synchronization device containing successively connected local oscillator and a delay line, whose outputs are connected to the first inputs of the coincidence unit, the corresponding outputs of the first unit are connected to the second inputs, and the outputs of the coincidence unit are connected to the corresponding inputs of the assembly unit. an additional block of matches, with the phasing signal applied to the reset input of the memory unit and to the input of the primary element, the output of which is connected to the same inputs of an additional the coincidence block, to the other inputs of which the corresponding outputs of the delay line are connected, and the outputs of the additional coincidence block are connected to the additional inputs of the assembly block, the outputs of which are connected to the corresponding installation inputs of the memory block.

The drawing shows the structural electrical circuit of the proposed device.

The phase synchronization device contains a series-connected local generator 1 and a delay line 2, the outputs of which are connected to the first inputs of a block of 3 matches, the second inputs of which are connected to the corresponding outputs of block 4, and the outputs of a block of 3 matches are connected to the corresponding inputs of the Assembly block 5. The device also contains a delay element b and an additional block 7 of coincidence, the phasing signal being fed to the reset input of memory block 4 and to the input of delay element 6, the output of which is connected to one input of the additional matching block 7, to the other inputs of which the corresponding line outputs are connected delays 2, and the outputs of the additional block 7 matches are connected to the additional inputs of the assembly block 5, the outputs of which are connected to the corresponding installation inputs of the memory block 4. The total output of assembly unit 5 is the output of the device.

The device works as follows.

The impulse of the local generator 1 arrives at the input of the delay line 2, at the outputs (outlets) of which the impulses successively appear, shifted one relative to the other by the time X rj / where T is the period of the impulses of the local generator 1, and

n is the number of taps of the delay line. A pulse of the phasing signal is fed to the input of the delay element 6 and to the reset inputs of the memory block 4 ,. resetting the memory. After a time equal to the delay time in the delay element 6, in block 7 of coincidence, the phasing pulse will coincide with the pulse of one of the taps of delay line 2. As a result, a pulse will appear at the corresponding output of block 7 of coincidence. Through block 5, this pulse is fed to the output of the device and to the corresponding setting input of block 4 of memory. Then the output of memory block 4 corresponding to this input is allowed pass

the next pulse of the local generator 1 through the block 3 matches from that tap of the delay line 2, the signal of which coincided with the phasing pulse

in block 7 matches. Thus, at the output of the device, pulses will appear, the phase of which is rigidly connected to the phase of the phasing pulse. Phasing pulses can occur.

Less often than local generator 1 pulses are a multiple of times, storing the phase in this interval provides memory block 4 by memorizing a tap of the delay line 2 corresponding to this phase. The presence of the backup element 6 is due to the need for the priority of resetting memory block 4 in time over the recording.

The proposed device reduces the loss of information when entering synchronism and improves the quality of data transmission.

Claims (2)

1. Authors certificate of the USSR 543181, cl. H 04 L 7/02, 1974. 2. For France No. 2167259, cl. q 03 B 3/00, q 08 C i9 / oo.