SU773945A1 - Device for mutual synchronization of communication system timing oscillators - Google Patents

Description

L of the frequency is connected to the third inputs of the comparison units of all channels through the polling pulse shaper, and the output of the controlled oscillator is connected to other inputs of the modulators.

The drawing shows a structural electrical circuit of the proposed device ..

: A device for mutual synchronization of communication network clock generators contains n channels, each of which consists of input key 1, control element 2, first frequency divider 3, phase discriminator 4, modulator 5, counter b, driver 7 rewriting pulses, key 8 , the memory block 9 and the comparison ID block, the second frequency divider 11, the sampler 12 of the polling pulses, the adder 13 and the generator 14 is controlled.

The mutual synchronization device of the communication network clock generators operates as follows.

One input of the input keys 1 is supplied with a clock frequency signal, which is separated in a node from the impulse streams of other nodes of the integrated communication network coming through the communication lines. These clock signals are also fed to one of the inputs of the control elements 2. The keys 1 are supplied with a control signal from one of the outputs of the control elements 2. The corresponding initial signals are fed through the inputs X, Y, Z of the control elements 2. installing the first dividers 3 and counters b to avoid the result of a false measurement at the initial ms time point. After setting the initial conditions of the first dividers 3 and counters 6, the inputs of the first dividers 3 receive the clock signals from the outputs of the input keys 1, After the first dividers 3 these signals are sent to one inputs of the phase discriminators 4, and to the other inputs the phase discriminators 4 receive a signal from the output the second divider 11. Phase discriminators 4 give signals about the phase difference between the clock pulses of the local oscillator and the oscillations of the selected sync signals of other nodes. These signals are fed to one of the inputs of the modulators 5, to the other inputs of which the local clock frequency is fed from the control output. generator 14. In modulator 5, the transformed phase difference signal of phase discriminators 4 goes to counters 6 in a pulse signal, and then to some inputs of keys 8. To other inputs of switches 8, a control signal is sent overwriting the result of the first measurement from the output of generator 7, as a result counter status 6 last

The first measurement is transferred to block 9 and the entire operation time of the device is stored there. The outputs of blocks 9 and counters 6 are connected to one input of blocks 10, to the other inputs of which a signal is sent that polls the output of the driver 12, which generates polling pulses after each subsequent cycle of measuring phase differences with phase discriminators 4. If the state of the counters 6 does not match block 9, then the output of the block 10 is the corresponding control signal. For example / if the contents of counters 6 are less than the contents of blocks 9, then block 10 generates a signal on the first output to reduce the frequency of the controlled oscillator 14, otherwise, when the contents of counters 6 are greater than the contents of blocks 9, the command appears at the second output about increasing the frequency of the controlled oscillator 14. If after the next measurement the contents of the counters 6 and blocks 9 are equal, then the command appears on the third outputs of block 10 and means that the adjustment of the controlled oscillator 14 is not needed From the outputs of blocks 10 of the control The phenomena are summed in adder 13, the result of which is equal, for example, to algebra and the sum of all incoming commands to its input. The algorithm of the adder 13 can be selected and logical. At the first output of the adder 13, the command about reducing the frequency of the controlled oscillator 14 appears, and at the second output about increasing the frequency. .

Since the change in the state of the counters b occurs only as a result of a change in the phase difference at the outputs of the phase discriminators 4, a constant delay time does not change this state and there are no trim commands at the output of the adder 13. The change in the state of the counters b occurs only under the influence of the difference in their own often clock oscillations of the controlled generator, oscillator 14, and input oscillations. This means that the frequency setting does not depend on the constant delay time of the communication lines, however, the synchronization accuracy of the controlled oscillator 14 will be high.

When connecting new lines of communication, the proposed device works as follows.

Before introducing a new line (new direction) or connecting a line that was being repaired through control element 2, it gives a signal of the initial installation to the first dividers 3 and counters b, then the input signal 1 through the input key 1

Claims (1)

Claim A mutual synchronization device for communication network clocks, containing η channels, each of which consists of an input key, a frequency divider and a phase discriminator connected in series, the control element is combined by the input with the input key, and its outputs are connected respectively to other inputs of the input key and the first divider frequency, as well as a series-connected adder, a controlled generator and a second frequency divider, the output of which is connected to other inputs of the control elements and phase discrimination ators of all j channels, characterized in that, in order to increase the accuracy of synchronization, a re-write pulse generator and sequentially connected modulator, counter, key, memory unit and comparison unit, as well as a polling pulse generator are introduced in each channel, and the outputs of the phase discriminator of each channel connected to the inputs of the modulator and driver for them 15 overwrite pulses, the output of which is connected to another input of the key, the input of which is connected to the second input of the comparison unit, the outputs of all comparison units are connected to the inputs of the adder, the output of the second frequency divider through the pulse shaper polling is connected to the third inputs of the comparison blocks of all channels, and the output of the controlled generator 25 is connected to other inputs of the modulators.