JPH01221249A - Control circuit of recording device - Google Patents

Abstract

PURPOSE:To make it possible to set the timing of a generation processing signal freely from outside by providing a parameter setting circuit consisting of a register and a comparator as an attachment to a timing circuit. CONSTITUTION:Registers 2-5 receive timing parameters from an external circuit as a clock count through signal lines 14-17, accumulate the values of the clock count, and output the accumulated data to comparators 6-9. Comparators 6-9 compare data entered from the registers 2-5 with an address value which is the count-up data of a basic clock generated in a counter 1. If both data agree to each other, a trigger signal is input to a timing generation circuit consisting of a vertical synchronous signal generation circuit 10, a horizontal synchronous signal generation circuit 11, a vertical enable signal generation circuit 12 and a horizontal enabled signal generation circuit 13. In each timing generation circuit, a timing signal of required shape for the control of an external circuit or a recording device is generated based on a trigger signal entered.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control circuit for a recording apparatus, and more particularly to a control circuit for an electrophotographic recording apparatus used in facsimiles, printers, and the like.

[Conventional technology]

Conventionally, the control circuit for this type of recording apparatus has been configured to control the recording speed, recording paper width, laser optical unit, LED recording head, and LC.
Since various design parameters differ depending on the type of recording head, etc., and are designed uniquely to the device, control signals such as image signals, horizontal synchronization signals, vertical enable signals, and horizontal enable signals are processed or output under fixed conditions. are doing.

For example, an apparatus that uses both A4 and 84 size paper is capable of processing and generating signals corresponding to A4 and 84 widths.

[The problem that the invention aims to solve]

The control circuit of the conventional recording apparatus described above primarily depends on the usage conditions of the hardware equipment used, so if the usage conditions differ even slightly, it is necessary to design a new one. In other words, there is a problem that it cannot be used under arbitrary hardware setting conditions.

This problem is particularly noticeable when the control circuit is implemented as an LSI, and each time the specification conditions such as recording speed, recording paper width, and type of recording head are changed and the hardware equipment of the recording device is developed. There are problems in that it requires an LSI development cost and a long development period.

[Means to solve the problem]

The control circuit of the recording apparatus of the present invention includes a counter circuit that counts up and outputs a basic clock, a register that stores parameters that instruct processing contents, and a trigger signal that outputs the output from the counter circuit according to data from this register. and a timing generation circuit that generates a timing signal necessary for a recording operation based on the trigger signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The counter 1 counts up and outputs a basic clock in order to determine the time sequence for this control circuit to process and generate signals.

Registers 2, 3, and 4.5 receive parameter inputs from an external circuit through signal lines 14°15, 16, and 17 using the timing parameters of instructions to be processed by this control circuit as clock numbers, and store the values. This accumulated data is output to comparators 6.7 and 8.9.

Comparators 6.7 and 8.9 compare the data input from registers 2 to 5 with the address value, which is the count-up data of the basic clock generated by counter 1, and when the two match, trigger signals are sent. is input to the timing generation circuit. In this embodiment, the timing generation circuit is a vertical synchronization signal generation circuit 10. Horizontal synchronization signal generation circuit 11, vertical enable signal generation circuit 12. A horizontal enable signal generation circuit 13 is illustrated.

Each timing generation circuit generates a timing signal necessary for controlling an external circuit or recording device based on the input trigger signal.

For example, the horizontal synchronization signal generation circuit 10 has a function of starting an internal timer composed of a flip-flop or the like by a trigger signal, and generating a pulse having twice the width of the basic clock using the timing of the trigger signal as a leading edge. have

With this configuration, data can be input from outside the control circuit, unlike conventional systems that consist of only a counter circuit and a timing generation circuit, which generates a fixed timing signal. Can generate timing signals.

For external parameter settings, a dedicated circuit may be provided and input may be made using a hardware method; You can also.

In addition, when the CPU uses 8-bit processing, the address data input to the register can be up to 28-bit.
Up to address 1, register 14.15.16.17
By providing an 8-bit register as a common register before and after the , and using it as a buffer, it is possible to set parameters up to address 2t61 by inputting the address data twice.6 For example, when recording A3 size width to 4
Even if it is recorded at a density of 80 dots/inch, it will be 5612
Since it is a dot, it can be set up to address 2t31.

Although this circuit can be constructed using individual components, it can also be constructed using LSI using techniques such as gate arrays.
This can be achieved on a scale almost equivalent to that of conventional circuits.

〔Effect of the invention〕

As explained above, the present invention provides a control circuit for a recording device having a counter circuit and a timing generation circuit, which includes a parameter setting circuit including a register and a comparator in association with the timing circuit. The timing of the generated processing signal can be arbitrarily set externally, and even if the specifications of the recording device's hardware equipment are changed, there is no need to change the same circuit.
Therefore, there is an effect that the development cost and development period can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. 1 to 5...Register, 6 to 9...Comparator,
DESCRIPTION OF SYMBOLS 10... Vertical synchronization signal generation circuit, 11... Horizontal synchronization signal generation circuit, 12... Vertical enable signal generation circuit, 13... Horizontal enable signal generation circuit, 14-17
...Parameter input signal line, 18...Vertical synchronization signal line, 19...Horizontal synchronization signal line, 20...Vertical enable signal line, 21...Horizontal enable signal line, 22.
...Oscillator.

Claims (1)

[Claims] A counter circuit that counts up and outputs a basic clock, a register that stores parameters that instruct processing contents, a comparator that outputs the output from the counter circuit as a trigger signal according to data from this register, and the trigger signal. 1. A control circuit for a recording apparatus, comprising: a timing generation circuit that generates a timing signal necessary for a recording operation.