JPH0537753A - Picture processor - Google Patents

Abstract

PURPOSE:To implement phase control not requiring much higher operating frequency of a phase control circuit (BD signal sampling and frequency divider) even when a picture transmission clock frequency is increased by eliminating a 1/n quantization error in existence at all times when the phase control is applied to a BD signal and the picture transmission clock. CONSTITUTION:When phase control is applied to a BD (beam detect) signal and a picture transmission clock and the BD signal rises, a picture transmission clock enable signal (CE) is active and the picture transmission clock is generated from a trigger signal respectively delayed from delay circuits 302-304 while the CE signal is active.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing device,
For example, in a laser beam printer of an electrophotographic process, when image transmission control is performed in synchronization with a main scanning direction synchronization signal (hereinafter referred to as “BD signal”), the image transmission clock is synchronized with the BD signal. The present invention relates to an image processing device that uses a method of performing phase control.

[0002]

2. Description of the Related Art Conventionally, in this type of apparatus, an oscillator having a frequency n times that of the image transmission clock is used to sample the leading edge of the BD signal and generate a pulse having a width of 1 / n of the period of the image transmission clock. However, the method of resetting the frequency divider with the pulse of 1 / n width and controlling the phase of the image transmission clock has been used.

Here, a conventional image processing apparatus and its operation timing will be described.

FIG. 6 is a block diagram showing a configuration of an image processing apparatus according to a conventional example, and FIG. 7 is a timing chart showing an operation mode of the image processing apparatus of FIG.

In FIG. 6, reference numeral 601 denotes a BD sample circuit for sampling a BD signal and generating an RST signal for resetting the frequency divider 602, and 603 is n times (n is a natural number) the image transmission clock (φ). It is an oscillator with a frequency. In FIGS. 6 and 7, an example of 8 times is described.

In FIG. 7, the BD signal is constantly sampled by an 8φ signal having a frequency eight times as high as the image transmission clock (φ), and when the BD signals meet, an RST having a pulse width corresponding to one clock of the 8φ signal. BD sample circuit 601
Will output. The frequency divider 602 receives the RST signal and resets the output signals 4φ, 2φ, φ in synchronization with the 8φ signal.
At this time, in FIG. 7, all become "H".

After that, the frequency divider 602 performs a counting operation, and each clock (4φ, 2φ, φ) operates as shown in FIG.

Here, in the example of FIG. 7, the phase difference between the BD signal and the image transmission clock (φ) is a maximum of 1/8 (n = 8) of the period of the image transmission clock.

[0009]

However, in the above-mentioned conventional example, the BD signal is transferred to the n of the image transmission clock.
Since the sampling is performed at twice the frequency, there is always a quantization error of 1 / n of the period of the image transmission clock, and the phase of the BD signal and the image transmission clock is always 1 / n of the period of the image transmission clock. There is a drawback that they are different, that is, the writing start position of the image fluctuates by 1 / n.

Furthermore, in order to reduce the above quantization error, n must be increased, which inevitably results in BD.
There is a drawback in that the circuit operating frequency of the signal sampling circuit and the frequency divider must be increased, and when the frequency of the image transmission clock becomes high, the circuit operating frequency must be increased similarly to the above.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and an object thereof is to always exist in the conventional example when performing phase control of a BD signal and an image transmission clock. In addition to eliminating the quantization error of / n, the phase control circuit does not need to raise the operating frequency of the phase control circuit (BD signal sampler and frequency divider) so much even if the frequency of the image transmission clock increases. The point is to provide an image processing apparatus capable of

[0012]

[Means for Solving the Problems]
In order to achieve the object, an image processing apparatus according to the present invention is connected to a printing apparatus, and in an image processing apparatus for obtaining an image transmission clock according to a main scanning direction synchronizing signal from the printing apparatus, image transmission according to an input trigger signal Setting means for setting the clock generation period, delay means for delaying the input trigger signal during the generation period set by the setting means, and trigger obtained by the delay means in accordance with the input main scanning direction synchronizing signal Generating means for generating an image transmission clock based on the signal.

[0013]

According to this structure, the setting means sets the generation period of the image transmission clock according to the input trigger signal, and the delay means delays the input trigger signal during the generation period set by the setting means to generate. The means generates an image transmission clock based on the trigger signal obtained by the delay means in accordance with the input main scanning direction synchronizing signal.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

(Description of Schematic Structure) FIG. 1 is a block diagram showing the structure of an embodiment of an image processing apparatus according to the present invention.
In FIG. 1, 101 is an image processing apparatus 102 of this embodiment.
Is a host computer for controlling the digital image data read from an image scanner (not shown).
No. 1 is stored in the image processing unit 1, and after being subjected to image processing such as window processing and movement processing, the image is transmitted to the image processing apparatus 102.

Reference numeral 103 is an image memory control block for temporarily storing the digital image data transmitted from the host computer 101. In the present embodiment, for example, a double line buffer configuration is adopted, and one scanning synchronization is established during image transmission between the host computer 101 and the image processing apparatus 102.

FIG. 2 is a timing chart showing an example of operation timing of image transmission according to this embodiment.

In FIG. 1 and FIG. 2, VCLK indicates image data from the host computer 101 to the image processing apparatus 10.
2, LSYNC is a sub-scanning synchronizing signal of the image processing apparatus 102, VE is a vertical image valid signal indicating an effective area of one image page, and HE is a horizontal image indicating an effective area of one scanning. The respective valid signals are shown. The communication line is used to transmit a command from the host computer 101 to the image processing apparatus 102, and the image processing apparatus 1
02 to the host computer 101 for status transmission. A communication control block 104 communicates between the host computer 101 and the image processing apparatus 102. A CPU 105 performs a series of control sequences of the image processing apparatus 102. Reference numeral 106 denotes an RO which stores a program for performing a control sequence of the CPU 105.
Reference numerals M and 107 respectively denote work RAMs necessary for performing the control sequence.

Reference numeral 108 denotes a phase control block, which controls the phase of the BD signal and the image transmission clock (φ) when the image transmission between the image memory control block 103 and the image forming block 109 is performed. It will be described later. 109 is a laser light source related to the electrophotographic process,
An image forming block for controlling a laser driver, a photosensitive drum, a transfer drum, and the like, 110 is a control signal of a polygon scanner for laser scanning and a synchronizing signal B in the main scanning direction.
A main scanning control block that generates a D signal, 111 is a sub-scanning control block for performing paper conveyance control, and rotation control of a photosensitive drum, a transfer drum, and the like, and 112 is an image processing apparatus 10.
2 shows a sequence / timing signal generating circuit for generating timing signals for a series of two control sequences.

Next, the structure of the main part of this embodiment will be described.

FIG. 3 shows a phase control block 1 according to this embodiment.
08 is a block diagram showing the configuration, FIG. 4 is a timing chart showing the operation mode of the phase control block 108 of FIG. 3, and FIG. 5 is a BD signal or a trigger signal (TRG-T) input in this embodiment. FIG. 7 is a diagram showing an example in which the image transmission clock operates for a predetermined period. The trigger signal is
This is a signal urged by the main CPU 105 as described later. In FIG. 3, reference numeral 301 designates a trigger signal (TRG-A) for energizing the delay circuit 302 and TRG- during a period in which CE (image transmission clock enable signal) is active.
Trigger switching circuit for outputting A signal, 302 is TRG-A
A delay circuit for generating a TRG-B signal after a lapse of a predetermined time (TA) from the rising edge of the signal, a 303 receives an output signal (TRG-B) of the delay circuit 302, and a trigger T
A predetermined time (TB) from the rising edge of the RG-B signal
A delay circuit for generating a TRG-C signal after the passage, 304 receives an output signal (TRG-C signal) of the delay circuit 303, and outputs a TRG-D signal after a lapse of a predetermined time (TC) from the rising edge of the TRG-C signal. A delay circuit 305 for generating is a flip-flop (hereinafter referred to as “F / F”) for receiving the TRG-B signal and the TRG-D signal and generating the image transmission clock (φ).

The delay circuit 302, the delay circuit 303, and the delay circuit 304 are set by the CPU 105 so that the respective delay times are TA, TB, and TC (see FIG. 4). The period of the image transmission clock (φ) is determined by the determination of the delay time.

Next, the delay time determining method will be described. In this embodiment, the delay circuit 302, the delay circuit 303,
Each of the delay circuits 304 is provided with a digital programmable delay generator such as AD9500 (registered trademark), and when a trigger signal is input, the delay time amount is set as shown in the equation (1). That is, T = Tpd + (N / 256) .Tf (1) where T is the amount of delay time, and N is a digital value of 8 bits.
Data (0 to 255), Tf is at full scale (N =
255) programmable delay amount, Tpd is N =
The minimum delay time when 0 (depending on the element) is shown.

From the above equation (1), the delay circuits 302 to 3
Each of the delay time amounts TA, TB, and TC of 04 is expressed by the following equation (2).
~ (4). That is, TA = Tpda + (I / 256) .Tfa ... (2) TB = Tpdb + (J / 256) .Tfb ... (3) TC = Tpdc + (K / 256) .Tfc ... (4). Here, the cycle of the image transmission clock is Tp = 20.
0 ns, Tfa = 200 ns, Tfb = 50 ns,
It is assumed that Tfc = 5 ns is set. In this case, the minimum delay time of each of the delay circuits 302 to 304 is 0.78 ns, 0.20 ns, 0.02, respectively.
ns. Since the minimum step of the AD9500 is 10 ps or more due to the limitation of the element, the third digit after the decimal point is rounded off. Further, suppose that Tpda = 5 ns and Tpdb =
If 6 ns and Tpdc = 7 ns, (TA +
To realize TB + TC) = Tp = 200 ns, I =
It is sufficient to set the data of 200, J = 125, K = 50.

Actually, I, J and K are determined by the following processing.

That is, prior to image transmission, the CPU 10
5 is set so that the TRG-A signal, which is the output signal of the trigger switching circuit 301 in FIG. 3, becomes the OR of both signals TRG-T and TRG-D, and as shown in FIG.
Section signal for measuring the image transmission clock at the rising edge of GT (CE signal: T during image data transmission)
The RG-A signal is set to be active or inactive, and the CE signal is set to be active for a predetermined time (when the number of transmitted image data is 3400 pixels, 3400).
X200 = 680000 ns period) Set to be active. Here, the time during which the CE is active is set by, for example, an internal timer (not shown) of the CPU 105 (5440 × 12 when the timer macro is 8 MHz).
The CE signal is set by the equation of 5 ns = 680000 ns). After that, the main CPU 105 activates TRG-T, counts the image transmission clock in the section where CE is active,
I, so that the number of image transmission clocks VN = 3400
Adjust J and K. Here, in the CE section, VN = 340
Counting 0 has an error of 200 ns ≦ image transmission clock period <200.6 ns (for example, I = 20).
A combination of 0, J = 125, K = 51 is also allowed).
That is, maximum {3400 / (3400-1)} · 100,
That is, the image is diffused to about 100.03%, but there is no problem in practical use.

As described above, when the setting of I, J, K is completed, the CPU 105 causes the TRG-A signal which is the output signal of the trigger switching circuit 301 to be the OR of the BD signal and the TRG-D signal. Set. Then, when the BD signal is input, the CE becomes active, and as shown in FIGS. 4 and 5, the image transfer clock (φ) is output during the period in which the CE is active at the cycle (TA + TB + TC) and the CE is inactive. Then, the output of the image transmission clock (φ) is stopped and the next BD is awaited.

By performing the above operation, the phase control of the image transmission clock (φ) is performed every time the BD signal is input as a trigger.

As described above, according to this embodiment,
By using the digital programmable delay generator, the fluctuation of the image tip is eliminated, and even if the frequency of the image transmission clock becomes high, the phase control circuit can be configured without making the operating frequency of the phase control circuit so hard. is there.

Now, in the above embodiment, in FIG.
Although the delay circuit 302 and the delay circuit 303 are configured to be variable, the present invention is not limited to this, and the delay circuits 302 and 303 have fixed values in advance, and the delay circuit 304 controls the image transmission clock cycle. The configuration may be such that fine adjustment is performed.

Further, if a delay circuit for fine adjustment is arranged in the latter stage of the delay circuit 302 described in the above embodiment, the cycle of the image transmission clock can be set more accurately.

The present invention may be applied to a system including a plurality of devices or an apparatus including a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0033]

As described above, according to the present invention,
Fluctuations at the tip of the image are eliminated, and even if the frequency of the image transmission clock becomes high, it is not necessary to make the operating frequency for phase control so hard.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a timing chart showing an example of operation timing of image transmission according to the present embodiment.

FIG. 3 is a block diagram showing a configuration of a phase control block 108 according to this embodiment.

4 is a timing chart showing an operation mode of the phase control block 108 of FIG.

FIG. 5 shows a BD signal or TRG-T in the present embodiment.
Is a diagram showing an example in which the image transmission clock operates for a predetermined period when is input.

FIG. 6 is a block diagram showing a configuration of an image processing apparatus according to a conventional example.

7 is a timing chart showing an operation mode of the image processing apparatus of FIG.

[Explanation of symbols]

101 host computer 101-1 memory 102 image processing device 103 Image memory control block 104 Communication control block 105 CPU 106 ROM 107 RAM 108 Phase control block 109 image formation block 110 Main scanning control block 111 Sub-scanning control block 112 Sequence Timing Generation Circuit 301 Trigger switching circuit 302, 303, 304 Delay generation circuit 305 F / F 601 BD sample circuit 602 frequency divider 603 n times frequency oscillator

Claims (2)

[Claims] 1. An image processing device connected to a printing device to obtain an image transmission clock in accordance with a main scanning direction synchronizing signal from the printing device, and setting means for setting a generation period of the image transmission clock in accordance with an input trigger signal. A delay means for delaying the input trigger signal during the generation period set by the setting means, and a generation for generating an image transmission clock based on the trigger signal obtained by the delay means in accordance with the input main scanning direction synchronization signal An image processing apparatus comprising: 2. The image processing apparatus according to claim 1, wherein the generation means includes means for stopping generation of the image transmission clock after the generation period set by the setting means has passed.