KR20010035627A - Frequency multiplier using delay line - Google Patents

Abstract

PURPOSE: A frequency multiplier using delay lines is provided to generate double video clocks synchronized precisely using a simple CMOS logic. CONSTITUTION: In a frequency multiplier, the first delay line(503) inputs a system clock pulse and delays clock pulses respectively by serial-connected n numbers of gate delays. The second delay line(508) inputs synchronous signals and delays the signals respectively by serial-connected n numbers of gate delays. A latch(504) latches the output signals of the respective gate delays included in the first delay line depending on the desired periods. An encoder(505) analyzes logic values of values stored in the latch and generates a delay control value which digitizes a gate delay location corresponding to a desired duty. A multiplexer inputs the output signals of the respective gate delay included in the second delay line, and selects and outputs one input signal depending on the delay control value. An exclusive OR gate(509) performs an exclusive-OR operation of the synchronous signal and the output signal of the multiplexer.

Description

Frequency multiplier using delay line {Frequency multiplier using delay line}

TECHNICAL FIELD The present invention relates to frequency multipliers, and more particularly to frequency multipliers using delay lines for generating precisely doubled video clocks using simple CMOS logic.

As shown in FIG. 1, in a printer system that inputs video data to be printed by a video clock VCLK and implements an image on paper through a laser diode, the resolution of the image quality output from the same paper is measured. In order to increase the density of image data, a higher density of the video clock is required. One way to increase the frequency of the video clock is to double the video clock VCLK to double the resolution.

The color printer shown in FIG. 1 converts image data to be printed from a PC into a bitmap image through the MCU 101, and temporarily stores it in the memory 102. FIG. Then, the bitmap image stored in the memory 102 is transmitted to the engine 104 via the video clock, and the transmitted bitmap image is printed on paper through the imaging lens 43 or the like.

The apparatus for doubling the video clock according to the prior art has a delayed VCLK (FIG. 4B) by delaying the asynchronous signal VCLK (FIG. 4A) using a constant gate delay 301 by the configuration as shown in FIG. When the VCLK and the delayed VCLK are applied to the input terminal of the exclusive OR gate 302, the output terminal generates the doubled VCLK (D_VCLK) as shown in the waveform shown in FIG.

However, when the gate delay 301 used here is composed of general CMOS logic, the delay time varies depending on temperature, power supply voltage, and various environments (processes), so the duty of D_VCLK is not constant. There is a problem of deteriorating the image quality of the printer, and in severe cases there was a problem that some of the VCLK is lost.

In addition, in the case where a deviation occurs in the duty of four doubled VCLKs in the case of generating each VCLK for four colors (Y, M, C, K) as in a belt type color printer, There was a problem that the image quality of the printer was deteriorated because these deviations of the duty could not be adjusted.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a frequency multiplier using a delay line for generating a double duty video clock of a constant duty regardless of a change in the surrounding environment (process).

1 is a configuration diagram of a color laser printer to which a frequency multiplier using a delay line according to the present invention is applied.

2 shows a line synchronizing signal and a page synchronizing signal for a sheet of a color laser printer.

3 is a block diagram of a frequency multiplier according to the related art.

4 is a timing diagram of main signals shown in FIG. 3.

5 is a configuration diagram of a frequency multiplier using a delay line according to the present invention.

6 is a timing diagram of main signals shown in FIG. 5.

In order to achieve the above technical problem, a frequency multiplier using a delay line according to the present invention is a device for multiplying a frequency of a synchronization signal by using a system clock pulse. A first delay line for each delay by a delay, a second delay line for inputting the synchronization signal, and a delay for each delay by n serially connected gate delays, and an output of each gate delay constituting the first delay line A latch for latching signals at predetermined intervals, an encoder for generating a delay control value digitizing a gate delay position corresponding to a desired duty by analyzing a logic value of values stored in the latch, and the second delay line Input the output signals of the respective gate delays, and And the output signal from the multiplexer for selecting and outputting one of the input signal by the control value and the synchronization signal and the multiplexer, characterized in that comprises the exclusive-OR gate for exclusive-or operation.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 5, the frequency multiplier using the delay line according to the present invention includes a pulse generator 501, an AND gate 502, a first delay line 503, a latch 504, an encoder 505, An accelerometer 506, a second delay line 508, and an exclusive OR gate 509 are provided.

The delay line 503 receives the doubled clock pulse CLK2X and is delayed by n gate delays constituting the delay line. In this case, it is effective to set the number n of gate delays to be larger than the time corresponding to 1/2 cycle of CLK2X and smaller than the time corresponding to one cycle of delay line 503. Here, the CLK2X is an oscillation clock generated using a crystal oscillation element or the like and is hardly influenced by an external environment such as temperature.

For example, suppose the CLK2X has a frequency of 50MHz and the standard delay of the gate delay is 1µSEC.

The value of the gate delay constituting the delay line 503 at the falling edge or rising edge, which is a position corresponding to one-half period of the CLK2X, is from ″ 1 ″ to ″ 0 ″ or ″ 0 ″. Switch to ″ 1 ″. Assuming that the gate delay has exactly 1μSEC delay time without any environmental influence, the half cycle of CLK2X is 10μSEC, so it outputs the same logic value from the 1st gate delay to the 10th gate delay, and at the 11th gate delay The logic value opposite to the 10th gate delay is output.

However, if the delay time is changed due to environmental effects such as temperature, voltage or process, the position of the gate delay in which the output value is inverted will be changed. Accordingly, the delay line 503 serves to inform the length or position of the 1/2 cycle of the CLK2X substantially in consideration of changes in the environment.

The latch 504 latches the outputs of the n gate delays constituting the delay line 503 for each period of the line sync signal Line_Sync or the page sync signal Page_Sync shown in FIG. 2. In an embodiment of the present invention, the latch is latched for each cycle of the line sync signal Line_Sync.

That is, the pulse generator 501 generates one pulse by the CLK2X every time the line synchronization signal is input. In addition, the output signal of the pulse generator 501 and CLK2X are applied to the input terminal of the AND gate 502, and the result is calculated by performing an AND operation on these input signals to generate a single pulse every time a line sync signal is generated. By applying to the clock CK terminal of the latch 504, the output values of the respective gate delays of the delay line 503 input for each cycle of the line synchronization signal are latched.

Then, the encoder 505 generates a delay control value for determining the duty of the video clock VCLK using the value of each gate delay stored in the latch 504.

That is, as shown in FIGS. 6A and 6B, when the frequency of CLK2X is set to twice the frequency of VCLK, one half of CLK2X corresponds to one quarter of VCLK. Thus, for example, in the case of doubling the duty of the VCLK at 50%, the logic value of the continuous gate delay corresponding to the position of the quarter cycle of the VCLK corresponds to the position value of the gate delay inverted. Generate a delay control value.

The adjuster 506 serves to correct a deviation of the doubled VCLK duty generated by an external application circuit. That is, an adjustment value (Adjust_Value) in consideration of the influence of the external environment is added or subtracted to the delay control value output from the encoder 505.

The second delay line 507 delays VCLK through each gate delay and is configured in pairs with the first delay line 503 to have the same characteristics. That is, it is composed of the same number of gate delays as the first delay line 503, has the same delay time, and the same amount of change according to temperature, voltage, and process (environment).

The multiplexer 508 inputs the output of each gate delay constituting the second delay line 507, selects an input gate delay according to the delay control value corrected by the adder / lower 506, and selects the VCLK delayed at the corresponding gate delay. Output it.

In other words, when the frequency of CLK2X is set to twice the frequency of VCLK, and the adjustment value is ″ 0 ″ to double the frequency of VCLK at 50%, the multiplexer 508 uses the encoder 505. A gate delay having a quarter cycle delay time output from the second delay line 507 is selected and output based on a delay control value indicating a gate delay position value corresponding to a quarter cycle of the output VCLK.

Accordingly, the MUX_OUT output from the multiplexer 508 corresponds to a 1/4 cycle delayed signal of the VCLK regardless of changes in the external environment according to temperature, voltage, and process as shown in FIG. 6C.

Performing an exclusive OR operation on the outputs of the multiplexer 508 and the MUX_OUT and VCLK by the exclusive OR gate 509 yields D_VCLK, which is a doubled VCLK with exactly 50% duty, as shown in FIG. do.

If it is not necessary to adjust the deviation of the 2-fold VCLK duty generated by the external application circuit, the regulator 506 is deleted and the delay control value of the encoder 505 is directly applied to the multiplexer 508. One of the gate delays input from the delay line 507 may be selected.

In an exemplary embodiment of the present invention, for convenience of description, the frequency of CLK2X is set to twice the frequency of VCLK, and the DVCVLK is generated to double the frequency of the VCLK at 50%. However, these setting values are changed. In other words, it is well known to those skilled in the art that the delay control value output from the encoder 505 can be achieved to change the duty accordingly.

As described above, according to the present invention, by using a pair of delay lines to generate a double duty video clock of a constant duty regardless of the influence of temperature, voltage, process (environment), etc. The deviation between the clock dutys that are doubling can be kept constant, thereby increasing the reliability of data transmission by the high frequency video clock.

Claims (7)

In the apparatus for doubling the frequency of the synchronization signal using a system clock pulse, A first delay line for inputting the system clock pulse and delaying each of them by n serially connected gate delays; A second delay line for inputting the synchronization signal and delaying each of them by n serially connected gate delays; A latch for latching output signals of each gate delay constituting the first delay line at predetermined intervals; An encoder for analyzing a logic value of values stored in the latch and generating a delay control value digitizing a gate delay position corresponding to a desired duty; A multiplexer for inputting output signals of the gate delays constituting the second delay line, and selecting and outputting one input signal according to the delay control value; And And an exclusive-OR gate for performing an exclusive-OR operation on the synchronization signal and the output signal of the multiplexer. The frequency multiplier of claim 1, further comprising an adder and attenuator for correcting a delay control value of the encoder by an adjustment value. The frequency multiplier of claim 1, wherein the first and second delay lines have the same characteristics. The frequency multiplier of claim 1, wherein the latch is latched at every line synchronization signal period. The frequency multiplier of claim 1, wherein the latch is latched at every page sync signal period. The frequency multiplier of claim 1, wherein the frequency of the clock pulse is set to twice the frequency of the synchronization signal. The method of claim 1, wherein the number n of gate delays constituting the first and second delay lines is one cycle in which the total delay time of the first and second delay lines is greater than a time corresponding to one half of the clock pulse. Frequency multiplier using a delay line, characterized in that the setting smaller than the time corresponding to.