JP3035817B2 - Clock recovery device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock reproducing apparatus for receiving a digital data signal and reproducing and outputting the clock signal.

[0002]

2. Description of the Related Art In a digital transmission line test system (error measurement, jitter tolerance measurement, etc.) or a digital signal relay system, a clock signal is converted from an input data signal to determine a binary of the input data signal. , And a data signal is read using the reproduced clock signal.

Conventional clock recovery devices used for such purposes include those of the free-running oscillation type and those of the filter type.

FIG. 6 shows a configuration of a conventional clock recovery device of a free-running oscillation system. This clock recovery device,
As shown in FIG. 7A, the pulse width of the data is equal to the bit period T and is equal to NRZ (non return ton).
This is for reproducing and outputting a clock signal from a data signal (hereinafter, referred to as an NRZ data signal) in a zero (Zero) format. (Hereinafter referred to as an RZ data signal).

The signal conversion circuit 11 comprises an OR / NOR circuit 12, a NOR circuit 13, and a delay circuit 14, one of the inputs of which are fixed to 0, and converts the NRZ data signal into an OR / N signal.
The other input terminal of the OR circuit 12 receives the signal, the OR output of the OR / NOR circuit 12 is input to one input terminal of the NOR circuit 13, and the NOR output of the OR / NOR circuit 12 is as shown in FIG. The delay circuit 14 delays the data signal by one-half of the bit period T and inputs the data signal to one input terminal of the NOR circuit 13. The NOR circuit 13 outputs the pulse width T as shown in FIG. / 2 RZ data signal is output to free-running oscillation circuit 15. Note that, when an NRZ data signal in which “1” continues is input, the signal conversion circuit 11 outputs data of “1” only for the last “1”.

The free-running oscillation circuit 15 includes an OR / NOR circuit 1
6 and a cable delay circuit 17 connected between one input terminal of the OR / NOR circuit 16 and the inverted output terminal. The other input terminal of the OR / NOR circuit 16 has the signal input terminal of the signal conversion circuit 11 connected thereto. Output is input. The delay time Td of the delay circuit 17 is set substantially equal to 1/2 of the bit period T of the data signal.

Therefore, when the level of the input RZ data signal is not "1" as in the initial stage of the operation, FIG.
As shown in FIG. 7D, the NOR output of the OR / NOR circuit 16 becomes "1" at a certain time t0, and after Td from its rise, as shown in FIG. Becomes "1", the NOR output of the OR / NOR circuit 16 becomes "0", and after Td, one input terminal returns to "0" and the NOR output returns to "1", and the above operation is repeated thereafter. Thus, the OR output of the OR / NOR circuit 16 has a period of 2 · Td (=
Self-running oscillation occurs at T).

When the "1" RZ data signal is input at time t1, the phase of the clock signal output from free-running oscillation circuit 15 matches the phase of the RZ data signal. However, the delay time Td of the delay circuit 16 does not completely coincide with 1/2 of the bit period T of the data signal, and the data signal also has phase jitter. , The phase shift is caused by the R of “1” as shown in FIG.
It is corrected every time the Z data signal is input.

In this way, by correcting the phase of the clock signal oscillated and output from the free-running oscillation circuit 15 with the RZ data signal, a clock signal substantially synchronized with each bit phase of the input NRZ data signal can be obtained. The NRZ data signal can be determined by this clock signal.

[0010]

However, in the conventional free-running type clock recovery apparatus described above, the upper limit of the data transmission rate depends on the response delay time of the OR / NOR circuit 16, its input terminal and its output terminal. Is directly limited by the distance between

That is, the delay time of the entire free-running oscillation circuit 15 is the sum of the delay time of the delay circuit 17 and the response delay time of the OR / NOR circuit 16 itself. In order to increase the data transmission rate, It is necessary to shorten the delay time of the entire free-running oscillation circuit 15. However, the OR / NOR circuit 1
6 itself is determined by the circuit element, and the cable length that determines the delay time of the delay circuit 17 is:
The distance can be reduced only to the distance between the input terminal of the OR / NOR circuit 16 and the NOR output terminal. In addition, in the case of a high-speed gate circuit, the input terminal and the output terminal are often separated from each other so as not to deteriorate input / output isolation.

For this reason, the conventional free-running oscillation type clock recovery apparatus described above has a limit of a transmission rate of 622 Mb / s, and it is extremely difficult to realize a higher transmission rate of 2.5 Gb / s. Was.

An object of the present invention is to provide a clock recovery device that solves these problems.

[0014]

In order to achieve the above object, a clock reproducing apparatus according to the present invention comprises: a data input terminal (20) for inputting a digital data signal; The data signal is delayed for an integer multiple of the bit period T of the data signal, and the delayed data signal is logically added to the data signal input to the data input terminal, and the data signal is input to the data input terminal. A delay addition circuit (22) for outputting a plurality of pulses including the input pulse at time intervals each time one pulse is input, a first input terminal receiving an output of the delay addition circuit, and a feedback signal The first input terminal outputs the logical sum of the signals input to the two input terminals of the second input terminal receiving the output, and outputs the inverted result of the logical sum from the second output terminal. A logic circuit (26), a signal output from the second output terminal of the logic circuit (2 · N + 1) T
/ 2 time (N is an integer equal to or greater than 1) delayed and input to the second input terminal of the logic circuit as a feedback signal (2
And a free-running oscillation circuit (25) that outputs a clock signal synchronized with a data signal input to the data input terminal from a first output terminal of the logic circuit.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows that the transmission rate f is 2.5 Gb
FIG. 2 is a diagram showing a configuration of a free-running oscillation type clock recovery device according to an embodiment for recovering a clock signal from a data signal of / s (bit period T = 1 / f).

In FIG. 1, a signal conversion circuit 21 is configured in the same manner as the signal conversion circuit 11 described above, converts an NRZ data signal input to a data input terminal 20 into an RZ data signal, and Output to

The delay addition circuit 22 includes a cable-type delay circuit 23 for delaying the output of the signal conversion circuit 21 for a time T, and an OR circuit 24 for logically adding the output of the signal conversion circuit 21 and the output of the delay circuit 23. Each time one pulse of the RZ data signal is input, one pulse is additionally output after T time from the input pulse. The delay circuit 23 delays the output of the signal conversion circuit 21 and inputs the output to the OR circuit 24.
Since the distance between the output of C.1 and the input of the OR circuit 24 can be shortened as much as possible in mounting, the delay time of the delay circuit 23 can be extremely reduced, and the delay for a high-speed data signal can be reliably performed. it can.

The output of the delay addition circuit 22 is
5 is input. The free-running oscillation circuit 25 has a two-input OR /
The NOR circuit 26 includes a cable type delay circuit 27 connected between one input terminal of the OR / NOR circuit 26 and the NOR output terminal. The OR / NOR circuit 26 is output from the delay circuit 27. Signal (feedback signal)
Is received at one input terminal, the output of the delay addition circuit 22 is received at the other input terminal, and its logical sum (OR) and its inverted result (NOR) are output. The delay time Td of the delay circuit 27 is (2N + 1) T / 2, where N = 1 and 3
It is set to T / 2.

FIG. 2 is a timing chart showing the operation of the clock signal reproducing device. Hereinafter, the operation of the clock signal reproducing device will be described based on this timing chart.

When an NRZ data signal "... 01010 ..." is inputted from the data input terminal 20 as shown in FIG. 2A, the NRZ data signal is outputted from the signal conversion circuit 21 as shown in FIG. An RZ data signal having the same data as the data signal and a pulse width converted to T / 2 is output.

The delay circuit 23 of the delay adder circuit 22, which has received the RZ data signal, outputs the pulse of "1" of the input RZ data signal with a delay of T time as shown in FIG. 2 (c). Therefore, as shown in FIG. 2D, the OR circuit 24 outputs a signal of four consecutive “1” s at T time intervals such as “... 011110.

On the other hand, in the initial state, that is, when no data is input to the data input terminal 20, the self-running oscillation circuit 25 has a timing at which the NOR output of the OR / NOR circuit 26 ((e) in FIG. 2) is present. After Td (3T / 2 hours in this example) after rising to "1", one of its input terminals rises to "1" as shown in (f) of FIG. 2 and the OR output ((g of FIG. 2) )) Becomes "1", the NOR output becomes "0", and after the time Td, the OR output returns to "0" and the NOR output returns to "1", so that 2Td (3T in this example). Self-running oscillation of a pulse signal with a period.

When three or more "1" pulses are successively input at time intervals T from the delay addition circuit 22, a clock signal having a period T synchronized with the pulse input from the delay addition circuit 22 is output. Outputs oscillation continuously.

That is, as shown in FIG. 2, the output of the delay circuit 27 of the free-running oscillation circuit 25 has an output (f) of "1" (3T / 2). Does not affect the operation of the free-running oscillation circuit 25, but "1" which is output second from the delay addition circuit 22
Pulse during the period when the output of the delay circuit 27 is “0” (3T
/ 2), and the width of the pulse (e) input to the delay circuit 27 is reduced by the second pulse. The narrow pulse is delayed by 3T / 2 and is input to one input terminal of the OR / NOR circuit 26. The narrow pulse is output as "1" from the delay addition circuit 22 for the third time.
OR / NOR circuit 26
Does not appear in the output of

Therefore, after the third pulse is output from the delay addition circuit 22, the output of the free-running oscillation circuit 25 becomes a clock signal having a period T and a duty ratio of 50,
The NRZ data signal can be read at the falling timing (or the rising timing).

As described above, the oscillation cycle of the free-running oscillation circuit 25 is drawn into the bit cycle of the input NRZ data signal, and a clock signal suitable for reading the NRZ data signal is oscillated and output. Thereafter, as shown in FIG. 2, even if a phase shift occurs between the input NRZ data signal (RZ data signal) and the clock signal,
Each time the NRZ data signal of “1” is input, the same pull-in operation as described above is performed, and the phase shift due to the jitter of the NRZ data signal and the delay time error on the clock recovery device side is corrected, and the NRZ data signal is always Oscillation outputs a clock signal that is optimal for reading data.

In FIG. 2, the NRZ data is "...
001100..., And “1” is continuously output twice from the delay adder circuit 22 as “... 0110...”, The first “1” is input to the free-running oscillation circuit 25. A pulse that is narrower (or wider) than T / 2 that is sometimes generated cannot be masked by the next input data of “1”, and the duty ratio of the clock signal output from the free-running oscillation circuit 25 does not become 50. Although a state occurs temporarily, the input of the next NRZ data signal of “101” causes the delay addition circuit 22 to output data of three or more consecutive “1” s to the free-running oscillation circuit 25 and output the clock signal. The duty ratio is modified to 50.

As described above, in this clock recovery device,
By adding one pulse to one pulse of the RZ data signal output from the signal conversion circuit 21 and inputting it to the free-running oscillation circuit 25, the delay time Td is set to three times the conventional value. , A clock signal synchronized with the input data is obtained.

Therefore, the OR / NO of the free-running oscillation circuit 25
A clock signal can be reliably reproduced and output from a data signal having a high transmission rate of 2.5 Gb / s without being directly limited by the delay time of the R circuit 26 or the distance between the input and output terminals.

Here, as an example of a device capable of increasing the transmission rate with the simplest configuration, a free-running oscillation circuit 25
Has been described with the delay time of 3T / 2, and the number of additional pulses output by the delay addition circuit 22 is 1. However, the delay time of the free-running oscillation circuit 25 is 3T / 2, and the delay addition circuit 2
The number of additional output pulses of 2 may be two or more. In this case, even when the RZ data signal “1” is input sporadically, three or more consecutive pulses are always input to the free-running oscillation circuit 25, so that the duty ratio of the clock signal temporarily varies. Is also reduced.

Further, if the number of added pulses of the delay addition circuit is further increased, a higher transmission rate can be handled. For example, like the delay addition circuit 32 shown in FIG. 3, delay circuits 23 ₁ and 23 ₂ whose delay times are set to T and 2T, respectively.
And a set of OR circuits 24 ₁ and 24 ₂ are connected in cascade so that three additional pulses are output per one input pulse. The delay time is set to, for example, 5T / 2.

Further, as in the delay addition circuit 42 shown in FIG. 4, T delay, respectively, 2T, the set delay circuits ₂₃ 1 to 23 ₃ and the OR circuit ₂₄ 1-24 ₃ set to 4T in tandem Connection, so that seven additional pulses are output per one input pulse, and the delay time of the free-running oscillation circuit 25 is set to, for example, 7T / 2 according to the increase of the additional pulses.
Set to. If the number of added pulses of the delay addition circuit is increased in this way, the delay time of the free-running oscillation circuit can be further increased, and a data clock signal having a higher transmission rate can be reliably reproduced.

The number of additional pulses of the delay addition circuit with respect to the delay time of the free-running oscillation circuit may be determined according to the frequency of occurrence of "1" in the input data. That is,
When the frequency of occurrence of “1” is high, the number of pulses output by the delay addition circuit including the input pulse may be smaller than 2N + 1. Conversely, when the frequency of occurrence of “1” is low, It suffices that the number of pulses output by the delay addition circuit including the input pulse is close to 2N + 1. Also, by completely masking the narrow or wide pulse generated at the time of retraction,
When it is necessary to output a clock signal with a duty ratio of 50, the delay time (2N + 1) T /
2, the delay addition circuit includes 2N +
What is necessary is just to comprise so that one or more pulses may be output.

The configuration of the delay addition circuit is not limited to the tandem type as described above.
T, ..., M · T time (M is an integer of 1 or more) delay to a plurality of delay circuits ₂₃ 1 to 23 one OR circuit outputs the _M 54
May be configured to be added and output.

In the above-described embodiment, the clock signal is reproduced after converting the NRZ data signal into the RZ data signal. However, this is not intended to limit the present invention. When an RZ data signal is input, the input data may be directly input to the delay addition circuit.

[0036]

As described above, the clock reproducing apparatus according to the present invention delays the data signal input to the data input terminal by an integral multiple of the bit period T of the data signal.
A logical addition of the delayed data signal and the data signal input to the data input terminal is performed, and every time one pulse of the data signal is input, a plurality of pulses including the input pulse are output at T time intervals. A delay addition circuit for outputting to the free-running oscillation circuit is provided, and the delay time of the free-running oscillation circuit is set to (2 · N + 1) T / 2 (N is an integer of 1 or more).

For this reason, the delay time of the free-running oscillation circuit can be set to be much larger than the transmission rate of the input data signal. The clock signal can be reliably reproduced and output from a data signal of a remarkably high transmission rate without being directly limited by the distance.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the embodiment;

FIG. 3 is a block diagram showing a modification of the main part of the embodiment.

FIG. 4 is a block diagram showing a modification of the main part of the embodiment.

FIG. 5 is a block diagram showing a modification of the main part of the embodiment.

FIG. 6 is a block diagram showing a configuration of a conventional free-running oscillation type device.

FIG. 7 is a timing chart showing the operation of a conventional free-running oscillation type device.

[Explanation of symbols]

 Reference Signs List 21 signal conversion circuit 22 delay addition circuit 23 delay circuit 24 OR circuit 25 free-running oscillation circuit 26 OR / NOR circuit 27 delay circuit 42 delay addition circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 7/033 H04L 25/40

Claims (1)

(57) [Claims] 1. A data input terminal (20) for inputting a digital data signal, and a data signal input to the data input terminal is time-delayed by an integral multiple of a bit period T of the data signal. Logical sum of the data signal thus input and the data signal input to the data input terminal, and each time a data signal is input to the data input terminal, a plurality of pulses including the input pulse are generated. A delay addition circuit (22) that outputs at a time interval T, and a logical sum of signals input to two input terminals of a first input terminal receiving an output of the delay addition circuit and a second input terminal receiving a feedback signal Is output from a first output terminal and the inverted result of the logical sum is output from a second output terminal, and is output from a second output terminal of the logical circuit. Signal 2 · N + 1) T / 2 hours (N
And a delay circuit (27) for delaying and inputting as a feedback signal to a second input terminal of the logic circuit, and a clock signal synchronized with a data signal input to the data input terminal. A clock recovery device comprising: a free-running oscillation circuit (25) that outputs from a first output terminal of the logic circuit.