JPH04302218A - Clock interruption detecting circuit - Google Patents

Abstract

PURPOSE:To make the clock interruption detecting circuit suitable for shortening time for detecting clock interruption, stabilizing the time and being composed of a digital integrated circuit. CONSTITUTION:A clock signal (a) and a timer clock signal (b) have the equal frequency and different phases. When the clock signal (a) is interrupted, an output (c) of a flip-flop 1 is turned to a low (or high) level. Since a flip-flip 1 is turned output (c) at this low level with the rise of the next clock signal (b), afterwards, the output (d) is turned to the low level. Since a flip-flop 3 latches this output (d) at the low level with the rise of the further next clock signal (b), afterwards, the non-inverted output is turned to the low level and therefore, an inverted output (e) is turned to the high level. As the result, the output of an EXOR gate 4 is turned to the high level, a flip-flop 5 latches the output with the rise of the clock signal (b) and a clock interruption detecting signal (f) as the output is turned to the high level.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock disconnection detection circuit for detecting disconnection of a clock signal.

0002

2. Description of the Related Art FIG. 3 shows an example of a conventional clock disconnection detection circuit. This circuit is composed of a monostable multivibrator 8, and when a clock signal is input to a terminal 10, it is triggered at the rising edge of the clock signal, and a low-level pulse whose duration is determined by the time constant of a resistor 6 and a capacitor 7 is T. is output to terminal 15. However, when clock signals are input one after another, the trigger is retriggered each time, and the output maintains a low level as long as the clock signals are input. Then, when the clock signal is cut off, the output changes to a high level when a time T has elapsed from the point in time when the immediately previous clock signal rose, and this means that the clock cutoff has been detected.

0003

[Problems to be Solved by the Invention] Such a clock loss detection circuit is often used in the field of general communications to monitor faults in working lines.In this case, the output signal of the clock loss detection circuit is It is used as a control signal to switch from a line to a protection line. Incidentally, when a fault occurs in the working line and the line is switched to the protection line, it is desirable that the time during which communication services are interrupted is as short as possible, and therefore clock interruption must be detected as quickly as possible.

However, when the conventional clock loss detection circuit is configured with a monostable multivibrator of a general-purpose integrated circuit as shown in FIG. It is difficult to set it to .

Although resistors and capacitors are used, these analog elements are an obstacle to converting the circuit into a digital LSI.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and to provide a clock interruption detection circuit which has a short clock interruption detection time, is stable, and is suitable for being constructed with a digital integrated circuit. be.

[0007]

[Means for Solving the Problems] The present invention provides a clock interruption detection circuit for detecting interruption of a clock signal, which includes a clock generation circuit that generates a timer clock signal having the same frequency as the clock signal but different in phase from the clock signal, and a first flip-flop whose output is inverted each time a signal is input; and a second flip-flop that latches the output of the first flip-flop each time the timer clock signal is input.
a third flip-flop that latches the output of the second flip-flop each time the timer clock signal is input, and an exclusive OR of the outputs of the second and third flip-flops. The fourth flip-flop is characterized in that it includes a gate that takes the value , and a fourth flip-flop that latches the output of the gate every time the timer clock signal is input.

[0008]

[Example] Next, an example of the present invention will be described. Figure 1
An example of a clock disconnection detection circuit according to the present invention is shown in FIG. This circuit is composed of flip-flops 1 to 3 and 5 and an exclusive OR gate 4. A terminal 10 is a terminal for inputting a clock signal a for detecting clock interruption, and is connected to a clock input 101 of the flip-flop 1. Inverted output 104 of flip-flop 1
is connected to the data input 102, and the non-inverting output 103 is connected to the data input 202 of flip-flop 2. The non-inverting output 203 of flip-flop 2 is connected to the data input 302 of flip-flop 3 and one input of exclusive OR gate 4, and the inverting output 304 of flip-flop 3 is connected to the other input of OR gate 4. It is connected. The output of exclusive OR gate 4 is connected to the data input 502 of flip-flop 5.
The non-inverted output 503 of is connected to the output terminal 15. Clock inputs 201, 3 of flip-flops 2, 3, 5
The timer clock signal b from the PLL circuit 20 is input to 01 and 501.

The PLL circuit 20 includes a phase comparison circuit 21, a filter 22, a voltage controlled oscillator 23, and a frequency dividing circuit 24.
It is made up of. The clock signal a is passed through the frequency dividing circuit 24
The phase is compared with the timer clock signal b which is the output of , and the result is given to the voltage controlled oscillator 23 through the filter 22, and the phase of the output signal is controlled. The output of the voltage controlled oscillator 23 is divided by the frequency dividing circuit 24 and outputted to the phase comparison circuit 21 and the flip-flops 2, 3, and 5 as a timer clock signal b having the same frequency as the clock signal a but different in phase. .

Next, the operation will be explained using the timing chart shown in FIG. First, when the clock signal a is input without interruption, the output c of the flip-flop 1 is inverted at the rising edge every time the clock signal a is input. The flip-flop 2 latches this output c at the rising edge every time the timer clock signal b is input, and as a result, the output d becomes as shown in the figure. Also, since the flip-flop 3 latches this output d at the next rising edge of the timer clock signal, its output is the output d shifted by one clock, so the inverted output e of the flip-flop 3 is as shown in the figure. . Since the exclusive OR gate 4 takes the exclusive OR of the output d and the output e, it is always at a low level, and the output of the flip-flop 5 that latches it, that is, the clock disconnection detection signal f, is also always at a low level. becomes.

On the other hand, if the clock signal a is cut off after the clock at timing t1, the output c of the flip-flop 1 becomes low level from timing t1 onwards. Flip-flop 2 latches this low level output c at the next rising edge b1 of timer clock signal b, so
After that, the output d also becomes low level. Moreover, since the flip-flop 3 further latches this low level output d at the next rising edge b2 of the timer clock signal b, its non-inverted output thereafter becomes a low level, and therefore the inverted output e becomes a high level. As a result, the output of the exclusive OR gate 4 becomes high level, the flip-flop 5 latches it at the rising edge b3 of the timer clock signal b, and its output, the clock interruption detection signal f, becomes high level and the clock interruption detection signal f becomes high level. occurrence will be notified. As can be seen from the timing chart, the clock interruption detection signal f becomes high level when a time T corresponding to 2.5 cycles of the clock signal a has elapsed after the clock interruption.
Although the case where the output c of the flip-flop 1 becomes low level due to clock interruption has been described as an example, the output of the flip-flop 1 may become high level depending on the timing at which the clock interruption occurs. However, even in that case,
Since the non-inverted output d of the flip-flop 2 and the inverted output e of the flip-flop 3 are always fixed at opposite logic levels, the output of the exclusive OR gate 4 changes to high level at the same timing.

0012

As described above, in the clock interruption detection circuit of the present invention, the clock interruption detection time corresponds to 2.5 cycles of the clock signal for which clock interruption is to be detected. Therefore, even if the clock signal is high speed, clock disconnection can be detected stably in a short time. As the clock signal becomes faster, the clock interruption detection time also becomes shorter, which is suitable for clock interruption detection of high-speed clock signals. Furthermore, since the circuit can be constructed from only logic elements, it is suitable for digital LSI implementation.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a clock disconnection detection circuit according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the clock interruption detection circuit of FIG. 1;

FIG. 3 is a circuit diagram showing an example of a conventional clock disconnection detection circuit.

FIG. 4 is a timing chart showing the operation of the clock interruption detection circuit of FIG. 3;

[Explanation of symbols]

1~3,5 Flip-flop 4 Exclusive OR circuit 10,15 Terminal 21 Phase comparison circuit 22 Filter 23 Voltage controlled oscillator 24 Frequency divider circuit

Claims (2)

[Claims] 1. A clock disconnection detection circuit for detecting disconnection of a clock signal, comprising: a clock generation circuit that generates a timer clock signal having the same frequency as the clock signal but a different phase; a first flip-flop whose output is inverted; a second flip-flop that latches the output of the first flip-flop each time the timer clock signal is input; and a second flip-flop that latches the output of the first flip-flop each time the timer clock signal is input; , a third flip-flop that latches the output of the second flip-flop, a gate that takes an exclusive OR of the outputs of the second and third flip-flops, and the output of this gate is connected to the timer clock signal. A clock disconnection detection circuit comprising a fourth flip-flop that latches each input. 2. The clock disconnection detection circuit according to claim 1, wherein the clock generation circuit is a PLL circuit.