JPH03104312A - Chattering preventing circuit - Google Patents

Abstract

PURPOSE:To reduce the scale of the hardware by allowing a logic circuit decoding the output of a digital switch to detect the presence of the relation between decode input and output, and latching specifically a decode output in response to its detection output. CONSTITUTION:An output comprising plural bits of a digital switch is decoded by a logic circuit 2 and the presence of a relation between decode output and input is detected by the circuit 2. Moreover, an output of the circuit 2 is latched by a 1st latch circuit 3 synchronously with the clock and a part corresponding to the relevantly detected decode input output among outputs of the circuit 3 and the clock are inputted to a gate circuit 5, from which the clock is outputted only when the relation exists. Then the part corresponding to the decode output among the outputs of the circuit 3 is latched by a 2nd latch circuit 4 synchronously with the circuit 5 to reduce one stage of the register.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a chattering prevention circuit that prevents chattering in digital switches used to set the operating modes of various devices, and aims to reduce the scale of hardware by using multiple bits. a logic circuit having a function of decoding the output of the digital switch having the switch and detecting whether or not the decoded output corresponds to the input before decoding; and a first latch that latches the output of the logic circuit in synchronization with a clock. A circuit, a portion of the output of the first latch circuit that corresponds to detecting whether or not there is correspondence between the decode input and output, and the clock are inputted, and the clock is output only when there is correspondence. and a second latch circuit that latches a portion of the output of the first latch circuit that corresponds to the decoded output in synchronization with the output of the gate circuit. There is.

[Industrial application field]

The present invention relates to a chattering prevention circuit that prevents chattering of digital switches used for setting operation modes of various devices.

Digital switches are often used to set the operating modes of various devices. The setting of such a digital switch is generally read by a digital circuit inside the device, but it is necessary to prevent the switch from chattering in order to avoid erroneous input.

[Prior art and problems to be solved by the invention] No. 4
FIG. 1 is a diagram showing an example of the structure of a conventional chattering prevention circuit.

In Fig. 4, 1 is a digital switch, 31, 32
, and 33 are registers, 34 is an OR circuit, 35 is a collation circuit, and 36 is a decoding circuit.

The output of a plurality of bits of the digital switch 1 is latched in the register 31 at the timing of the rising edge of the clock, and latched in the register 32 at the timing of the next rising edge. Then, the output of the wealth register 32 is applied to the input terminal of the register 33.

The output of the register 31 and the output of the register 32 described above are input to the collation circuit 35, and it is determined whether the two match. If they match, the matching circuit 35 outputs an enable signal EN at L level. The enable signal EN is applied as the other input of the OR circuit 34, which applies the clock as one input.

The output of the OR circuit 34 is the output of the register 32 applied to the input terminal of the register 33.
gives the timing to be latched to. That is, unless the enable signal EN outputted from the collation circuit 35 becomes L, the output of the digital switch 1 will be output from the register 33.
is not latched.

When the output of the digital switch 1 becomes stable and the output of the matching circuit 35 becomes L, the output of the digital switch 1 is latched in the register 33, and the output of the register 33 is further decoded by the decoding circuit 36. The operation mode set in the digital switch l is decoded and becomes a corresponding control signal inside the device.

However, the structure shown in FIG. 4 has a problem in that the scale of the hardware is large.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a chattering prevention circuit with reduced hardware scale. [Means for solving the problem] Figure 1 shows the basic structure of the present invention. In FIG. 1, l is a digital switch, 2 is a logic circuit, 3 and 4 are first and second latch circuits, respectively, and 5 is a gate circuit.

The logic circuit 2 has a function of decoding the output of the digital switch 1 having a plurality of bits and detecting whether or not the decoded output corresponds to the input before decoding.

The first latch circuit 3 latches the output of the logic circuit 2 in synchronization with a clock.

The gate circuit 5 inputs the clock and a portion of the output of the first latch circuit 3 that corresponds to the detection of the presence or absence of correspondence between the decode input and output, and detects the correspondence only when the correspondence exists. Output clock.

The second latch circuit 4 latches a portion of the output of the first latch circuit 3 that corresponds to the decoded output in synchronization with the output of the gate circuit 5.

[Effect]

The operation of the structure shown in FIG. 1 is almost the same as that of the structure shown in FIG. 4 described above, but in the structure shown in FIG. functions are combined into one logic circuit 2, and the number of registers is also reduced by one stage.

Therefore, the hardware scale is reduced.

〔Example〕

FIG. 2 shows the structure of an embodiment of the present invention.

In FIG. 2, 21 is a 4-bit digital switch, 22 is a ROM, 23 and 24 are registers, and
25 is an OR circuit.

The ROM 22 implements the logic circuit 2 shown in FIG.
3 and 24 respectively realize the first and second latch circuits 3 and 4 in FIG. 1, and the OR circuit 25 realizes the gate circuit 5 in FIG. The 4-bit output of the digital switch 2l is applied to the 0th to 3rd bits of the ROM 22, and the ROM 22 decodes the content of the 4 bits and outputs it as a 6-bit output (decoded) signal, which is the 1st to 6th bits in this example. . The 6-bit decode signal is latched in the register 23 in synchronization with the clock, and the portion of the output of the register 23 corresponding to the 6-bit cough is again output to the RO.
It is applied as input to the 4th to 9th bits of M22.

In addition to the decoding function described above, the ROM 22 also has a function as a verification circuit, and outputs the first to sixth bits and the fourth bit.
~ Determine whether the 9 bits of human power match. If they match, the eighth bit of the output is set to L level, and after being latched in the register 23, it is applied as an enable signal to one input of the OR circuit 25.

A clock is applied to the other input of the OR circuit 25, and the output of the OR circuit 25 is applied to the edge trigger input terminal of the register 24.

Therefore, the register 24 can receive a clock at the edge trigger input terminal only when the enable signal is at L level, and can latch data applied to the input terminal at the timing of the clock.

In this way, the output of the digital switch 1 is latched in the register 24 and appears as an output only when the output of the digital switch 1 becomes stable and the eighth bit of the output of the ROM 22 becomes L.

Since the output of the register 33 is a decoded signal that was previously decoded in the ROM 22, the operating mode set in the digital switch 1 is decoded and becomes a corresponding control signal within the device.

FIG. 3 shows an example of the timing of the configuration shown in FIG.

In FIG. 3, the output of the digital switch 21 is changed from A to C.
The timing of the operation is shown when chattering indicated by ゜“B” occurs during the change to .

Since the output EN of the ROM 22 corresponding to the enable signal is L only when the decoded output of the ROM 22 and the corresponding output of the register 23 match, the output corresponding to the enable signal EN of the register 23 is as described above. After the period in which no match is obtained ends, it becomes L at the next rising edge of the clock. Then, at the timing of the next rising edge of the clock, the decode output C' corresponding to the changed switch output C is latched in the register 24 (until the timing of the latch is reached, the output of the register 24 is is the switch output A before the above change
remains the decoded output A' corresponding to ). [Effects of the Invention] According to the chattering prevention circuit of the present invention, the scale of hardware can be reduced.

[Brief explanation of drawings]

Figure 1 is a basic configuration diagram of the present invention, Figure 2 is a configuration diagram of an embodiment of the present invention, Figure 3 is a timing diagram of the configuration shown in Figure 2, and Figure 4 is a diagram of the conventional configuration. FIG. 3 is a diagram showing an example of the structure of a chattering prevention circuit. [Explanation of symbols]

Claims (1)

[Claims] 1. A logic circuit (2) having a function of decoding the output of a digital switch (1) having a plurality of bits and detecting whether or not the decoded output corresponds to the input before decoding. , a first latch circuit (3) that latches the output of the logic circuit (2) in synchronization with a clock, and whether or not there is correspondence between the decode input and output of the output of the first latch circuit (3). a gate circuit (5) that inputs the part corresponding to detection and the clock and outputs the clock only when there is a correspondence; A chattering prevention circuit comprising a second latch circuit (4) that latches a portion corresponding to the decoded output in synchronization with the output of the gate circuit (5).