SU1695514A1 - Decoder - Google Patents

Abstract

The invention relates to computing and can be used in the construction of decoding devices in information transmission systems. The invention allows not only to decode informational messages, but also to detect errors in them. The decoding device contains blocks 1 and 7 of memory, element 2 EXCLUSIVE OR NOT, inverter 3, element OR 4, element EXCLUSIVE OR 5, trigger 6. 3 Il. 1 tab.

Description

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The invention relates to computing and can be used in the construction of decoding devices in information transmission systems.

The purpose of the invention is to enhance the functionality of the device by providing error detection.

FIG. 1 shows a functional block diagram of the device; in fig. 2 - time diagrams of the device operation with error-free message transmission; in fig. 3 - the same, when an error occurs in the alternation of 3/6 and 6/3 combinations, when an incorrect 6/3 combination from among the allowed combinations is transmitted on the third bar instead of the 4/5 (5/4) combination.

The device contains the first memory block 1, the element 2 EXCLUSIVE OR-NOT 2 the inverter 3, the element OR 4, the element EXCLUSIVE OR 5, the trigger 6 and the second memory block 7. Positions 8 and 9 denote, respectively, the information and clock inputs of the device, positions 10 and 11, respectively, the information outputs and the error output of the device.

FIG. 2 and 3 corresponding indices denote the following signals: a is the signal at the input 9 of the device; b, c, d-signals, respectively, on the first, second, and third outputs of the memory block 7; d - signal at the output of the trigger 6; e is the signal at the output of element 2; W - signal at the output of element 5; h - signal at the input of the inverter 3; and - the signal at the output of the inverter 3; K - signal at the output 11 of the device.

Memory unit 1 is implemented on a programmable read-only memory (PROM). Memory unit 7 is implemented on the EPROM and is programmed so that according to the input words 9B, signals corresponding to the signs Disabled combination (Combination), Combination 6/3 and Combination 3/6 are generated at its outputs. The form of firmware PROM is given in the table.

The designation of the 6/3 and 3/6 outputs of memory block 7 in the table means that the combination of 6/3 or 3/6 corresponds to the formation of the O signal at the corresponding output of block 7.

The decoding device operates as follows.

The inputs 8 receive information in code 9B, and the clock input 9 receives the synchronization signal. Block 1 converts code 9B into information in code 8B, which is fed to outputs 10.

When error-free transmission of information at the first output of block 7, a signal O is produced, which is fed to the first input of the element OR 4. At the second and

the third output of block 7, when transmitting combinations 6/3 (3/6) or 7/2 (2/7), produces signals O and 1 (1 and O), respectively, and when transmitting combinations 4/5 (5/4), signals 1 In the first case, the trigger 6 is set to the one (zero) state by the synchronization signal, and in the second case, by the signals 1 at the inputs J and K, the state of the trigger 6 is preserved. With the arrival of the next combination of 3/6 (6/3) or 2/7 (7/2), which, in accordance with the specified alternation of combinations, should have the inverse ratio of zeros and ones, the signal O (1) goes to

5 the first input of the EXCLUSIVE or 5 element, at the second input of which a logical 1 (O) signal is set from the output of the trigger 6. At the same time, the EXCLUSIVE OR 5 output of the element is generated

0 signal 1, which through the inverter 3 logic O arrives at the second input of the element OR 4, and the trigger 6 is set to the zero (one) state by the synchronization signal, which is maintained for 5 s until the next combination 6/3 (3/6) or 7/2 (2/7).

According to the zero logic signals at the inputs, the OR 4 element generates an error O at the output 11 of the error, which corresponds to zero transmission of information.

When a forbidden combination occurs at the first output of block 7, signal 1 is generated, which through the OR 4 element enters error output 11, which corresponds to the appearance of an error in the transmitted information.

When an error occurs in the alternation of a combination of 3/6 (6/3) or 2/7 (7/2) at the second and third outputs of block 7, the signals O and 1 (1 and O) are generated, respectively, the signal 1 (O) arrives At the first input of the EXCLUSIVE OR 5 element, but at the same time, at its second input, a signal 1 (O) is set from the trigger output of trigger 6. By the same two logical signals at the inputs of the EXCLUSIVE OR 5 element, a signal O is generated at its output. output element EXCLUSIVE OR NOT 2

0 when transmitting combinations of 3/6 (6/3) or 2/7 (7/2) - according to logic signals at inputs O and 1 (1 and O) - signal O is generated. As a result, inverter 3 will generate signal 1, which through element OR 4

5 arrives at error output 11, which corresponds to the appearance of an error in the transmitted information.

Claims (1)

DETAILED DESCRIPTION A decoding device comprising a first memory block, the outputs of which are information outputs of the device, characterized in that, in order to expand the functionality of the device by providing error detection, an EXCLUSIVE OR NOT element, an EXCLUSIVE OR element, an inverter, an OR element, a trigger and a second memory block, the first output are inserted into the device which is connected to the first input of the element OR, the second output of the second memory block to the first input of the element EXCLUSIVE OR NONE and to the J input of the trigger, the output of which is connected to the first input of the element EXCLUSIVE OR, the third output of the second memory block is connected to the K-input of the trigger, with the second input of the EXCLUSIVE OR element and with the second input of the EXCLUSIVE element OR NOT, the output of which is combined with the output of the EXCLUSIVE OR element and connected via an inverter to the second input of the OR element, the output of which is the output of the device error, the inputs of the first the memory unit is combined with the corresponding inputs of the second memory unit and are the information inputs of the device, the trigger synchronization input is the clock input of the device. 10 11 12 Table continuation 6/3 41S No. b / 6 C15 US 6/3 4/5 OtuuSxa 6/3 4 / 5-6 / 3 3 / C US 4/5 f / 3 H & (