JPS6411484A - Decoding circuit - Google Patents

Decoding circuit

Info

Publication number
JPS6411484A
JPS6411484A JP62166841A JP16684187A JPS6411484A JP S6411484 A JPS6411484 A JP S6411484A JP 62166841 A JP62166841 A JP 62166841A JP 16684187 A JP16684187 A JP 16684187A JP S6411484 A JPS6411484 A JP S6411484A
Authority
JP
Japan
Prior art keywords
output
difference
mode
added
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62166841A
Other languages
Japanese (ja)
Inventor
Yoshiji Nishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62166841A priority Critical patent/JPS6411484A/en
Publication of JPS6411484A publication Critical patent/JPS6411484A/en
Pending legal-status Critical Current

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  • Compression Or Coding Systems Of Tv Signals (AREA)

Abstract

PURPOSE:To display a difference mode with a high reliability and to constitute a hardware easily by sharing an IC by constituting a mode display part of one bit adder in which the output of a transition detecting part is defined to be an input and an added output to be a mode display signal. CONSTITUTION:At the time of receiving difference code data Din including a transition code TR in the transition detecting part 11, a transition detecting output appears, and '1' is impressed to a first input of the adder 21. Then, it is added to a second input, namely, an input obtained by feeding back an output state '1' or '0' until then. Accordingly, the output of the adder 21, namely, the mode display signal M is alternately inverted for every detection of the transition code in such a manner of 0 1 0 1.... A data reproducing part 14 reproduces data according to a difference mode. When the first difference mode I is designated by the mode display signal M, the difference data of respective picture element is accumulated and added to obtain an output Dout. On the contrary, when the second difference mode II is designated, the difference data is accumulated and added at an interval of a picture element to obtain the output Dout.
JP62166841A 1987-07-06 1987-07-06 Decoding circuit Pending JPS6411484A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62166841A JPS6411484A (en) 1987-07-06 1987-07-06 Decoding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62166841A JPS6411484A (en) 1987-07-06 1987-07-06 Decoding circuit

Publications (1)

Publication Number Publication Date
JPS6411484A true JPS6411484A (en) 1989-01-17

Family

ID=15838643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62166841A Pending JPS6411484A (en) 1987-07-06 1987-07-06 Decoding circuit

Country Status (1)

Country Link
JP (1) JPS6411484A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007507182A (en) * 2003-09-25 2007-03-22 ピアレス・システムズ・コーポレーション Divided run-length encoding method and apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007507182A (en) * 2003-09-25 2007-03-22 ピアレス・システムズ・コーポレーション Divided run-length encoding method and apparatus

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