SU1037234A1 - Data input device - Google Patents

Abstract

A DEVICE FOR INPUT OF INFORMATION, containing a serially connected register and the first (Element And the output of which is the first output of the device, and the first input of the register 51 is the first input of the device, the second and third And elements, the first input of the Second And element , the OR element and the counter, the first input of which is connected to the second input of the register, characterized in that, in order to increase the reliability and simplify the device, a delay element is inserted in it, the input of which is connected to the first input the house of the counter, the second input of the first element And with the output of the second element And, the second input of which is connected to the output of the counter and the second input of the third element And, the output of which is connected to the second input of the counter, and the first input of the third element And is connected to the output of the element OR the first input of which is connected to the output of the delay element, and the second input of VL is the g second input of the device, the output tn of the second element I is the second output of the device. with

Description

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Figure 1 The invention relates to computerized automation and can be used in control systems operating in a time division mode. A device for controlling the transmission of information is known, comprising a generator of sync pulses, a clock generator, triggers of microoperations to information registers, and a clock pulse generator connected to sync pulse generator and microfoam triggers, which are connected to information registers C13. A disadvantage of this device is its complexity. The closest in technical essence to the proposed is a device for entering information, containing a generator synopulse, information register, four elements AND the OR element, a counter, two arshtera 23 A disadvantage of the known device is its complexity, which consists in using a large number of construc items. In addition, in the known device, tight synchronization is required, which are fed to the inputs of the device of control pulses with TaKTOBbnvra clock pulses. If this condition is not fulfilled for some reason, a device malfunction may occur and erroneous information is introduced, i.e. Yci has also low reliability. The purpose of the invention is to simplify the device and improve the reliability of its operation by reducing the number of structural elements included in it and eliminating the clock generator. The goal is achieved by the fact that a register and a first O are connected to a device for inputting information (the element I, the output of which is the first output of the device, and the first input of the register is the first input of the device, the second to the third elements I, input The second e-mail AND is connected to the input of the third element AND, the OR element and the counter, the input of which is connected to the second input of the register, the delay element is input, the input of which is connected to the first input of the counter, the second input of the first element I and V And the second input of which is connected to the output of the counter and the second input of the third element AND, the output of which is connected to the second input of the counter, - and the first input of the third element And is connected to the output of the OR element, the first input of which is connected to the output of the delay element, and the second The input is the second input of the device, the output of the second element I is the second output of the device. Fig. 1 shows the functional electrical circuit ycTpojteTBa for the input of information in FIG. 2 is an example of an information registry. The device (figure 1) contains (information) register 1, the first element And 2, the counter 3, the second element And 4, the delay element 5, the element OR in, the third element And 7, input 8, outputs 9 and 10, multiplexer 11 binary counter 12. Information register 1 is used for sequential output of information bits of input codewords and may consist, for example, of multiplexer 11, to the control of whose inputs are connected the corresponding outputs of binary counter 12. Discharge are supplied to the information inputs of multiplexer 11 transmitted code words. If the code word contains h information bits, then multiplexer 11 should have m control 1 x x inputs, where msBoQj n. The device works as follows. If the information p & 1 has a code word to be inputted, input 8 starts the input information input signal, which has the form of a single pulse. This pulse passes to the gate of the element OR 6, goes to the second inputs of the second and third elements AND 4 to 7. In the initial state of the gavi, at the output of the counter 3, there is a low sweat signal, which causes the pulse from the output of the element OR 6 to pass at the output of the second element 1 and 4, and is fed to the second input of the first element 1 2 and 2. If there is a high potential at the information register 1 output, this impulse passes to the output 9. If the low potential is at the output of the information register 1, the first element 2 of 1fy and specified momentum on Exit 9 does not pass. Thus, the code of the single bit of information is transmitted by two pulses on two output buses 9 and 10, the code of the zero bit of information is transmitted by only one pulse on the output lOi. The pulse from the output of the second element 4 is input to the information register at the output of which This is formed by the order of the information bit of the code word (on the back 4 line of the incoming impulse). The specified pulse also goes to the first counter 3, changing the state by one (by it (1FONT of the pulse), and through the delay element 5 to the second input element OR 6, the passage to the output of the next and the next to the second inputs, second and second If the low potential is present at the output of the counter, this impulse passes to the output of the second element I 4 n and goes to the second input of the first element I 2, the water of the next bit of information occurs. The infrared pulse from the output of the expensive element 4 is fed to the input of the information p & gispra 1, which goes to the next information heading, and so on. After entering the last bit, inform the code word when the next pulse arrives at the first input of the counter 3, after it overflows and a high potential is established at its output. At the same time, the next pulse arriving at the second inputs of the second and third elements I 4 and 7, passes to the output of the third element I 7 and goes to the second input of counter 3, dropping the latter into zero cocTOjb. The entry of information ends there. Other code words are passed with similarly. The transmitted code words have the form of a sequence of pulses, and the presence of a pulse in the next cycle at the output 9 of the device corresponds to a single bit of information, the absence of a zero bit of information. The pulse period in the sequence is determined by the delay on the delay element 5 and can vary within wide limits. Compared with the known device, the invention contains a smaller number of structural elements, which reduces the cost and increases the reliability of information input devices developed on its basis. Due to the fact that there is no sync pulse generator in the notion, no trigger input is required for the synthphone, which increases the reliability of the device. In addition, the pulse period in a pulse sequence can vary widely by choosing a specific delay element, which expands the functionality of the device.

Claims (1)

DEVICE FOR INFORMATION INPUT, containing a register connected in series and a first element AND whose output is the first output of the device, and the first input of the register is the first input of the device, the second and third elements AND, the first input of the second element AND is connected * to the first input of the third element AND , OR element and counter, the first input of which is connected to the second input of the register, characterized in that, in order to increase reliability and simplify the device, a delay element is introduced into it, the input of which is connected to the first input counter, the second input of the first element And and with the output of the second element And, the second input of which is connected to the output of the counter and the second input of the third element And, the output of which is connected to the second input of the counter, and the first input of the third element And is connected to the output of the OR element / the first input of which is connected to the output of the delay element, and the second input is g is the second input of the device, the output of the second element And is the second output of the device. Phi 1-1 SU-1037234>